Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

23-27 Sept. 1996

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  • Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit [front matter]

    Publication Year: 1996, Page(s):I - IX
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    Freely Available from IEEE
  • Author index

    Publication Year: 1996, Page(s):325 - 326
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    Freely Available from IEEE
  • A parallel test generation for combinational circuits based on Boolean satisfiability

    Publication Year: 1996, Page(s):267 - 270
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    This paper presents an efficient parallel algebraic algorithm to implement ATPG for combinational circuits using the Boolean satisfiability on a distributed computing environment. The Path-Oriented Expanded Implication Graph (POEIG) of a combinational circuit is taken as a heuristic guide to improve the traditional stochastic calculation of the Boolean satisfiability formula of a circuit. We propo... View full abstract»

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  • Low power design of two-dimensional DCT

    Publication Year: 1996, Page(s):309 - 312
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper discusses several techniques used in reducing power for a two-dimensional discrete cosine transform (2D DCT) design. These techniques include removal of circuit blocks that computes the DCT coefficients which will be quantized to zeros, re-ordering of operations in constant-multipliers to reduce transition probability, and re-designing cells for low-voltage operation. An 8×8 2D DC... View full abstract»

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  • Differential PSK detector ASIC design for direct sequence spread spectrum radio

    Publication Year: 1996, Page(s):97 - 101
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In this paper we present an optimized architecture for differential PSK detection which effectively minimizes the required logic complexity for ASIC implementation. This complexity reduction is obtained by carrying out intelligent truncation of the detector input words and by utilizing a bit-serial/word-parallel structure. We also show that this can be done without degrading the performance in ter... View full abstract»

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  • An efficient path-delay fault simulator for mixed level circuits

    Publication Year: 1996, Page(s):263 - 266
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results pr... View full abstract»

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  • Reducing power dissipation in low voltage flash memories

    Publication Year: 1996, Page(s):305 - 308
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A new low voltage flash circuit model is presented. This SPICE model is used to identify techniques for reducing the average power dissipated in a flash memory during a programming cycle. The AND flash memory cell is used in this analysis. For a selected bitcell in a NOR block, the power dissipated is dominated by a band-to-band transient current. SPICE simulations show that this power can be redu... View full abstract»

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  • A flexible direct sequence integrated receiver with ARM core

    Publication Year: 1996, Page(s):93 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    A single-chip digital direct-sequence spread-spectrum (DS SS) receiver ASIC, called DIRAC (Direct-sequence integrated Receiver with ARM core) is presented. Thanks to the programmability, the ASIC can be used in a wide variety of communication systems like the mobile satellite business network (MSBN) from the European space agency (ESA), PRODAT and IRIS. Key features are the integration of an ARM c... View full abstract»

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  • Efficient error bit identification from failing signatures

    Publication Year: 1996, Page(s):259 - 262
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Efficient identification of bit errors in the input to single and multiple input signature registers is obtained using a characteristic polynomial constructed from the product of multiple polynomials. This set of multiple polynomials may be primitive and/or non-primitive but must have different orders. The degree of the input polynomial to the signature register is limited to the least common mult... View full abstract»

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  • Testing in a mixed-signal world

    Publication Year: 1996, Page(s):241 - 244
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Wide differences in test signals used for analog and digital circuits make a common test for a mixed-signal device difficult. A divide and conquer strategy partitions the circuit into three types of blocks: analog, digital logic and memory. A design for testability structure using boundary scan and analog test bus allows very effective test application. With this design, separate specialized tests... View full abstract»

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  • Low-power design technique for ASICs by partially reducing supply voltage

    Publication Year: 1996, Page(s):301 - 304
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing one to reduce power without performance degradation. As a result of application to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capa... View full abstract»

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  • Design of integrated RF bandpass filters and oscillators for low-power radio receivers

    Publication Year: 1996, Page(s):87 - 91
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Full integration of radio receivers requires technology for implementing on-chip RF/IF bandpass filters and local oscillators. Analysis indicates that filter/oscillator designs operating in the VHF to L-Band frequency range are possible at low levels of power consumption if on-chip inductors are admitted into the design process. A prototype, fully-integrated LC oscillator operating at 200 MHz is r... View full abstract»

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  • Circuit partitioning for distributed VHDL fault simulation

    Publication Year: 1996, Page(s):255 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Switch-level faults, as opposed to traditional gate-level faults can more accurately model physical failures found on an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing distributed switch-level fault simulation using a novel switch-level circuit partitioning technique. Transistor reverse l... View full abstract»

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  • Multichip module placement with heat consideration

    Publication Year: 1996, Page(s):175 - 178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    A new algorithm for multichip module placement, MPH, using a combined quad-partitioning, genetic search and simulated annealing approach is presented here. In addition to minimizing wire length and vias, the algorithm places chips so that heat is evenly distributed over the substrate. The proposed algorithm obtains better solutions in less time than the simulated annealing and min-cut algorithms o... View full abstract»

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  • Sampling based design verification using design error models

    Publication Year: 1996, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A new simulation based design verification system employing design error models and statistical sampling techniques, is developed. It provides a simulation coverage which can be used as a guide in the verification process, and estimates the coverage quickly using sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient desi... View full abstract»

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  • Pixel cache architecture with FIFO implemented within an ASIC

    Publication Year: 1996, Page(s):19 - 22
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Implementation technology for 3D pixel cache and performance evaluation of a graphics processor Truga001, with 12 embedded processors within a single chip, are described. The chip can render 4 million vectors/s (10 pixels/vector) or 1.2 million triangle polygons/s (100 pixels/polygon) with Phong shading, texture mapping and hidden surface removal. A pixel-array configured with 8(x)×4(y)&time... View full abstract»

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  • VLSI design of the reassembly management for ATM/AAL

    Publication Year: 1996, Page(s):115 - 118
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The reassembly management is one of the key components in the ATM receiving function. To achieve high memory efficiency, we adopt a shared memory approach with the linked-list structure to support the ATM/AAL reassembly management. The chip with the die size 6570×6490 μm 2 and packaged in a 144-pin CQFP is fabricated by using TSMC 0.8 μm SPDM N-well CMOS technology. The desi... View full abstract»

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  • New architecture for high throughput-rate real-time 2-D DCT and the VLSI design

    Publication Year: 1996, Page(s):219 - 222
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PL... View full abstract»

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  • A 400 megasample per second digital receiver ASIC

    Publication Year: 1996, Page(s):235 - 238
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    An application specific integrated circuit has been designed to perform digital quadrature demodulation and other signal processing functions on digitized IF data in electronic warfare receivers. A fully pipelined, parallel architecture implemented on a GaAs gate array permits a nominal sampling rate of 400 megasamples per second. At this sampling rate the -3 dB bandwidth exceeds 80 MHz View full abstract»

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  • Opportunities for non-dissipative computation [adiabatic logic]

    Publication Year: 1996, Page(s):297 - 300
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Recent advances in adiabatic or non-dissipative computation, as reflected in conceptions of novel static and dynamic energy recovery logic families, are described. The energy, power and peak power of these logic families are compared with conventional static and dynamic CMOS. Key challenges to successful implementation of adiabatic systems are summarized View full abstract»

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  • Verification of ASIC designs in VHDL using computer-aided reasoning

    Publication Year: 1996, Page(s):163 - 166
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The paper describes verification of a 32-bit processor chip using formal reasoning. The VHSIC Hardware Description Language (VHDL) code for the processor and its components have been proven to meet the formal specification which uncovered interesting specification ambiguities and design errors. The paper provides an early evaluation of the role of formal reasoning in the verification of VHDL desig... View full abstract»

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  • Challenges and trends in RF design

    Publication Year: 1996, Page(s):81 - 86
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    This paper describes the challenges and trends in today's RF industry. Beginning with a brief look at the wireless communications environment, we examine receiver architectures and their building blocks from the point of view of monolithic integration. We then present trends in circuit and architecture design, device and technology development, and wireless infrastructures View full abstract»

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  • A 60 MHz 0.7 mV-resolution CMOS comparator

    Publication Year: 1996, Page(s):279 - 282
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    This paper describes the design of a CMOS comparator for high-speed data communication. The comparator consists of two regenerative sense amplifiers working in a pipelined fashion to achieve high speed. It operates from a single +5 V supply and is able to resolve 0.7 mV at 60 MHz sampling rate using a 0.9 μm CMOS process View full abstract»

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  • An alternative view on weighted random pattern testing

    Publication Year: 1996, Page(s):251 - 254
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper describes a new and highly efficient approach for weighted random test pattern generation. In contrast to the state-of-the-art approaches, where input specific weights are computed, the proposed self-test method is tuned on the computation of global, pattern oriented weights: with each weight the generation of the related random test patterns is uniquely specified. The proposed self-tes... View full abstract»

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  • A unified placement algorithm to improve both performance and area through sliceable partitions

    Publication Year: 1996, Page(s):183 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    A new placement approach integrating the legal placement arrangement into a combined method of global placement and constrained partitioning for simultaneous optimization of performance and area aspects based on slicing enumeration is presented. With the proposed placement approach the partitioning is constrained to sliceable partitions. This allows the control of critical nets and ensures legal p... View full abstract»

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