# [1992] Proceedings The European Conference on Design Automation

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Displaying Results 1 - 25 of 94
• ### Proceedings. The European Conference on Design Automation (Cat. No.92TH0414-3)

Publication Year: 1992
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• ### Functional testing of modern microprocessors

Publication Year: 1992, Page(s):350 - 354
Cited by:  Papers (2)
| | PDF (428 KB)

In the early 1980s, a method was developed for functional testing of microprocessors. Modern microprocessors have a functionality, such as on-chip caches, which is not covered by that model. This paper extends that functional model and proposes fault models, together with tests for such modern microprocessors. The proposed concepts and algorithms have been applied to the Intel i860 microprocessor ... View full abstract»

• ### Parametric ASIC-design by CADIC

Publication Year: 1992, Page(s):267 - 271
Cited by:  Papers (1)
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Large ASIC's often include regular blocks such as memories, arithmetic units and random logic. The design system CADIC enables a comfortable description of small and large blocks by a graphic interface. The paper describes experiences in the design of an ASIC chip implementing an efficiently testable floating point adder. By help of this example it is shown that CADIC combines both kinds of logic.... View full abstract»

• ### A clock net routing algorithm for high performance VLSI

Publication Year: 1992, Page(s):343 - 347
Cited by:  Papers (1)  |  Patents (6)
| | PDF (428 KB)

Presents a new algorithm, called FSTM (feasible segment tree method'), for the clock net routing of high performance VLSI designs. To avoid the clock skew, FSTM constructs a binary tree such that for each internal vertex of the tree, the cardinality of its sub-trees are balanced and the distances to its children are equal. The authors evaluate their results in terms of wire length and delay time ... View full abstract»

• ### A pragmatic approach to the automation of the logic design process

Publication Year: 1992, Page(s):262 - 266
Cited by:  Papers (2)
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The paper describes a logic-design system and its associated methodology used in developing the BULL DPS7000 mainframe system. The originality of the work lies in the methodology that integrates a set of state-of-the-art logic synthesis and formal verification techniques to make an effective logic-design system to support an iterative synthesis process View full abstract»

• ### Planning strategies for area routing

Publication Year: 1992, Page(s):338 - 342
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The area routing problem, solved with two meta-planning strategies (graceful retreat and least impact), is presented in this paper. These strategies are used to effectively manage the selection of net segments and the assignment of track resources. Many examples extracted from the literature are experimentally tested and most of layout results are better than other routers View full abstract»

• ### Advanced ordering and manipulation techniques for binary decision diagrams

Publication Year: 1992, Page(s):452 - 457
Cited by:  Papers (7)  |  Patents (1)
| | PDF (500 KB)

Heuristics leading to improved ordering computation for binary decision diagrams (BDDs) are given. An initial step, based on the topology of the network, generates a hierarchical variable ordering. This initial result is further refined by incremental manipulation governed by the stochastic evolution technique. A new property of BDDs is introduced as well, which accelerates commonly used operation... View full abstract»

• ### DAC-A silicon compiler system for high performance DSP ASIC

Publication Year: 1992, Page(s):257 - 261
Cited by:  Papers (1)
| | PDF (356 KB)

An overview is given of an application-specific silicon compiler system called DAC for the automated design of high performance DSP ASIC chips. This system consists of a number of application-specific silicon compilers and a set of universal utilities for the running and programming of these compilers. It provides an environment to systematically develop application-specific silicon compilers View full abstract»

• ### An automatic layout generator for analog circuits

Publication Year: 1992, Page(s):513 - 519
Cited by:  Papers (16)  |  Patents (4)
| | PDF (580 KB)

A design by example' approach to automatic layout generation for analog circuits is presented. This approach uses a sample layout, the template, to graphically capture an expert's knowledge of analog device placement and routing for a given module type. To generate a module, one supplies the required electrical parameters for each device and a geometrical constraint on the module's shape e.g. a d... View full abstract»

• ### Flow-a concurrent methodology manager

Publication Year: 1992, Page(s):20 - 24
Cited by:  Papers (2)
| | PDF (408 KB)

The Flow system is used to define methodology for ULSI design tasks in a formal way. It provides a concurrent environment in which such tasks are carried out automatically. The automatic execution of tasks in the Flow system utilize a set of workstations as computing resources. This paper describes the motivation for the development of Flow, the semantics used for methodology definition and the Fl... View full abstract»

• ### An error decoder for the Compact Disc player as an example of VLSI programming

Publication Year: 1992, Page(s):69 - 74
Cited by:  Papers (14)
| | PDF (480 KB)

Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI knowledge is nee... View full abstract»

• ### Parallel sequence fault simulation for synchronous sequential circuits

Publication Year: 1992, Page(s):434 - 438
Cited by:  Papers (5)
| | PDF (396 KB)

A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm partitions a given test sequence into subsequences of equal length and then performs fault simulation with these subsequences in parallel. To overcome the state dependency of sequential circuits, a multiple-pass method is developed to use minimal simulation passes. The experim... View full abstract»

• ### An efficient method for decomposition of multiple-output Boolean functions and assigned sequential machines

Publication Year: 1992, Page(s):114 - 122
Cited by:  Papers (9)
| | PDF (624 KB)

Since today's complex digital systems and circuits are difficult to design, optimize, implement and verify, decomposition methods and tools have attracted great interest recently. The objective of the new decomposition method presented in this paper is to implement a complex Boolean function or an assigned sequential machine with a minimal number of constrained building blocks and minimal connecti... View full abstract»

• ### Synthesis and optimization of synchronous logic circuits from recurrence equations

Publication Year: 1992, Page(s):226 - 231
Cited by:  Papers (8)
| | PDF (488 KB)

The paper presents a general solution framework for optimizing synchronous networks across register boundaries. It formulates the problem as that of finding minimum-cost solutions to synchronous recurrence equations. It proposes an algorithm for the solution of such equations that relies on their transformation into a new combinational logic optimization problem. An exact solution algorithm for th... View full abstract»

• ### Data configuration in an object oriented persistent programming environment for CAD

Publication Year: 1992, Page(s):404 - 409
Cited by:  Papers (2)
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Evaluates a methodology based on the object-oriented and persistent paradigms for the interfacing of CAD tools with a framework with emphasis on rapid prototyping. This combination ensures that all objects (design data) may be manipulated in a uniform manner, are virtual and possess object-oriented characteristics, be they of a volatile or persistent nature. In such a methodology, configuration is... View full abstract»

• ### Transfer free register allocation in cyclic data flow graphs

Publication Year: 1992, Page(s):181 - 185
Cited by:  Papers (4)
| | PDF (404 KB)

Discusses an algorithm for the optimal register allocation problem in cyclic data flow graphs. Cyclic data flow graphs result from high level behavioral descriptions that contain loops. Algorithms published up till now did not consider cyclic data flow graphs specifically. When these algorithms are applied to data flow graphs with loops, unnecessary register transfer operations may be introduced. ... View full abstract»

• ### Improved port assignment on channel boundaries

Publication Year: 1992, Page(s):333 - 337
Cited by:  Papers (1)
| | PDF (444 KB)

Deals with the task of assigning the crossing of nets on channel boundaries in the layout integration of macro cells. The author's approach to this problem targets both global criteria (overall area, net lengths) and local criteria (improved channel routability). This is done in a two-stage algorithm. In the first stage, all global needs are captured. In the second, all conflicting needs are resol... View full abstract»

• ### A synthesis for testability technique for PLA-based finite state machines

Publication Year: 1992, Page(s):361 - 365
Cited by:  Papers (1)
| | PDF (452 KB)

Proposes a method of testable synthesis in which a test function is incorporated into the state diagram of the object machine. The authors constrain logic minimization such that a fault has predictable effect on the composite machine (object machine embedded with the test function). This allows effective use of the test function, even when both object and test machines are faulty. A valid test seq... View full abstract»

• ### Analog behavioral models for simulation and synthesis of mixed-signal systems

Publication Year: 1992, Page(s):464 - 468
Cited by:  Papers (6)  |  Patents (1)
| | PDF (344 KB)

A behavioral simulator is shown to be an essential part of a performance-driven hierarchical top-down design strategy for analog blocks within mixed-signal integrated systems. It is used to accurately estimate the performance of the system while down-mapping the specifications over the hierarchy, in order to avoid time-consuming design iterations. It is also indispensable for the final bottom-up v... View full abstract»

• ### Parallelism extraction and programme restructuring of VHDL for parallel simulation

Publication Year: 1992, Page(s):81 - 87
Cited by:  Papers (3)
| | PDF (468 KB)

The authors obtained an overall increase in parallelism during VHDL simulation by decomposing simulation models into smaller computational units to be executed in parallel and by parallelizing the simulation support functions. The authors implementation targeted massively parallel architectures. Simulation experimentation and instrumentation was done on the SIMD Connection Machine View full abstract»

• ### Variable ordering for binary decision diagrams

Publication Year: 1992, Page(s):447 - 451
Cited by:  Papers (8)
| | PDF (448 KB)

Considers the problem of variable ordering in binary decision diagrams (BDD's). The authors present several heuristics for finding a good variable ordering based on the algebraic structure of the functions. They provide a non-interleaving theorem and an accurate cost formula for the optimal ordering. They treat the output ordering problem when a given circuit has multiple outputs and propose new h... View full abstract»

• ### Automatic synthesis of large Moore sequencers

Publication Year: 1992, Page(s):237 - 244
Cited by:  Papers (2)
| | PDF (624 KB)

The automatic synthesis of large Moore sequencers is performed on architectures whose novel features include the use of a ROM, a partitioned micro-sequencer on standard cells and a masking technique which restricts the computation of next state codes to significant bits. Extensive experiments have shown the efficiency of the approach in terms of both area and speed compared with a full standard ce... View full abstract»

• ### A data flow graph exchange standard

Publication Year: 1992, Page(s):193 - 199
Cited by:  Papers (20)  |  Patents (1)
| | PDF (568 KB)

Presents a data flow graph exchange standard, agreed upon and used by the partners in the ESPRIT research project, ASCIS. These data flow graphs are generated from known user interface languages such as Silage, VHDL, and C, and are used to drive architectural synthesis packages and formal verification. The graph semantics are defined to offer a unique degree of freedom for time and area optimizati... View full abstract»

• ### Design automation of power integrated circuits in EDGE environment

Publication Year: 1992, Page(s):252 - 256
Cited by:  Papers (2)  |  Patents (11)
| | PDF (360 KB)

Presents SETIPIC, a software package to forecast the electrothermal interactions in the first design steps of power integrated circuits. To give a well-consistent interface with graphic tools to the designer, SETIPIC works under the EDGE CAD system. The software aspect of this integration into EDGE is explained. PICMOST, the thermal simulator used by SETIPIC to obtain the thermal distribution on t... View full abstract»

• ### Automatic jog insertion for 2D mask compaction: a global optimization perspective

Publication Year: 1992, Page(s):508 - 512
Cited by:  Papers (1)  |  Patents (3)
| | PDF (388 KB)

A novel approach is presented to global optimization in 2D symbolic layout compaction based on `branch and bound' optimization, including automatic overconstraint resolution and jog insertion. The main characteristics are: an efficient generation in 2D of a nearly irredundant set of simple X and Y, diagonal and user constraints; incremental event-driven longest path calculation with positive cycle... View full abstract»