Proceedings 13th IEEE VLSI Test Symposium

April 30 1995-May 3 1995

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  • Proceedings 13th IEEE VLSI Test Symposium

    Publication Year: 1995
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    Freely Available from IEEE
  • Testability of floating gate defects in sequential circuits

    Publication Year: 1995, Page(s):202 - 207
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB)

    The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable bra... View full abstract»

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  • Author index

    Publication Year: 1995
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    Freely Available from IEEE
  • On the design of at-speed testable VLSI circuits

    Publication Year: 1995, Page(s):290 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    In this paper, a new design-for-testability technique for sequential circuits is presented. This technique may be considered as an alternative to full scan. The fault coverages obtained with this technique are comparable to those produced by full scan techniques. However, the present method improves full scan in several ways. The application test time of a device is reduced to that of applying par... View full abstract»

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  • High level fault modeling of asynchronous circuits

    Publication Year: 1995, Page(s):190 - 195
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A method is proposed for high level fault modeling of asynchronous circuits which are described by the signal transition graph. Transitional fault models are introduced. It is shown that the transitional faults are the direct mappings of most of the low level faults View full abstract»

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  • A partial scan methodology for testing self-timed circuits

    Publication Year: 1995, Page(s):283 - 289
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault cove... View full abstract»

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  • The concept of resistance interval: a new parametric model for realistic resistive bridging fault

    Publication Year: 1995, Page(s):184 - 189
    Cited by:  Papers (58)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 Ω to 500 Ω. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible,... View full abstract»

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  • Structural constraints for circular self-test paths

    Publication Year: 1995, Page(s):486 - 491
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Constraints on the structure of circular self-test paths in register transfer level (RTL) circuits with circular Built-In Self Test (BIST) features are discussed. These constraints arise from the desire to avoid bit-level correlation, which can have a devastating effect on test quality. Two causes of bit-level correlation are examined, with examples demonstrating the resulting degradation in test ... View full abstract»

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  • Testing combinational iterative logic arrays for realistic faults

    Publication Year: 1995, Page(s):35 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficien... View full abstract»

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  • Partial scan designs without using a separate scan clock

    Publication Year: 1995, Page(s):277 - 282
    Cited by:  Papers (5)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Existing flip-flop selection and test generation methods for partial scan designs assume the use of a separate scan clock. With a separate clock for the scan operation, the states of the non-scan flip-flops can be frozen during the scan operation and any state can be scanned into the scan register without affecting the states of the non-scan flip-flops. Under this assumption, test vectors can be e... View full abstract»

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  • Diagnostic of path and gate delay faults in non-scan sequential circuits

    Publication Year: 1995, Page(s):380 - 386
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns delay fault diagnosis for non-scan ... View full abstract»

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  • Compact test generation for bridging faults under IDDQ testing

    Publication Year: 1995, Page(s):310 - 316
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    We propose a procedure to generate compact test sets for bridging faults under IDDQ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of li... View full abstract»

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  • RT level testability-driven partitioning

    Publication Year: 1995, Page(s):176 - 181
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    This paper presents a method of partitioning RT level designs based on testability analysis results. The partitioning is carried out in two steps: (1) the data path of a design is partitioned at some hard-to-test points detected by the testability analysis algorithm. These points are made directly accessible by some DFT techniques; and (2) the control part of a design is modified to operate in two... View full abstract»

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  • VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits

    Publication Year: 1995, Page(s):221 - 226
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    VISION is an efficient parallel pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient parallel pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the parallel pattern fault simulation for synchronous sequential circuits. According to our expe... View full abstract»

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  • An approach for system tests design and its application

    Publication Year: 1995, Page(s):448 - 453
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An approach for system test design is suggested and justified by the corresponding mathematical model. It is based on the representation of a testing process in an aggregate form of two dynamically interacting components: a control testing table and a testing processor. Control testing tables are equivalent to linear programs which process Boolean arrays. It is proved that the correctness problem ... View full abstract»

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  • An experimental evaluation of the differential BICS for IDDQ testing

    Publication Year: 1995, Page(s):472 - 480
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    In this paper we present an experimental study on the effectiveness of IDDQ testing using the differential built-in current sensor (BICS) circuit. Two new test chips were designed and fabricated implementing a CMOS version of the 74181 ALU chip. In copies of this circuit we included the capability of activating 45 different “realistic” CMOS faults: inter- and intra-layer sho... View full abstract»

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  • Signature analysis and aliasing for sequential circuits

    Publication Year: 1995, Page(s):118 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    Many built-in self-test techniques insert test registers and thus segment the circuit into subcircuits which are surrounded by test registers. If not all registers of the circuit are enhanced to test registers, the resulting subcircuits are sequential. Errors in their test responses generally depend on the state of the subcircuit and hence can be correlated both in space and in time. In this paper... View full abstract»

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  • Cyclic stress tests for full scan circuits

    Publication Year: 1995, Page(s):89 - 94
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxonomy of stress related problems for full scan circuits is presented. It ... View full abstract»

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  • A distance reduction approach to design for testability

    Publication Year: 1995, Page(s):158 - 163
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    The average distance between states is proposed as a new testability measure for finite state machines (FSMs). Also proposed is the concept of center state to reduce distances in FSMs. This test function embedding technique has been shown to improve the testability of sequential circuits with minimal overhead. An overview of several design for testability (DFT) and synthesis for testability (SFT) ... View full abstract»

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  • A portable ATPG tool for parallel and distributed systems

    Publication Year: 1995, Page(s):29 - 34
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The use of parallel architectures for the solution of CPU and memory critical problems in the electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms the reduced portability of the code, and the cost of the hardware. However, portable message-passing libraries are now available, and the same code runs on high-cost supercomputers, as well as on commo... View full abstract»

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  • Asynchronous multiple scan chains

    Publication Year: 1995, Page(s):270 - 276
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    The long test application times needed for scan designs increase the costs of testing. In this paper we introduce the concept of asynchronous multiple scan chains in which groups of scan chains operate independently. This is achieved by using more than one made signal to control the scan flip-flops. Asynchronous multiple chains can provide large reductions in the test application time. We present ... View full abstract»

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  • Generation of high quality tests for functional sensitizable paths

    Publication Year: 1995, Page(s):374 - 379
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Some previously published results show that in a number of combinational circuits a significant portion of long paths is neither robustly nor non-robustly testable. However, not all of those untestable paths may be ignored in delay testing. Functional sensitizable paths are robust and non-robust untestable but, under some faulty conditions, may degrade the performance of the circuit. Even though t... View full abstract»

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  • Test pattern generation for IDDQ: increasing test quality

    Publication Year: 1995, Page(s):304 - 309
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    So far, the test pattern generation for IDDQ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during t... View full abstract»

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  • A solution for the on-line test of analog ladder filters

    Publication Year: 1995, Page(s):48 - 53
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    In this paper we study stability problems associated with the previously developed design for test (DFT) methodology applied to ladder filters. A solution based on simple modification of the basic DFT strategy is proposed which allows on-line testing of ladder filters. A filter example demonstrates the feasibility of the solution View full abstract»

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  • Detecting IDDQ defective CMOS circuits by depowering

    Publication Year: 1995, Page(s):324 - 329
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    When disconnecting the power supply line of a CMOS circuit in its quiescent state, the capacitances present in the circuit hold the logic valves in all their nodes. In non defective circuits, these capacitances discharge very slowly due to the extremely small IDDQ discharge current. On the other hand, in IDDQ defective circuits the discharge is faster than in the previous cas... View full abstract»

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