Proceedings. Fifth Great Lakes Symposium on VLSI

16-18 March 1995

Filter Results

Displaying Results 1 - 25 of 53
  • Proceedings. Fifth Great Lakes Symposium on VLSI

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (267 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (95 KB)
    Freely Available from IEEE
  • A personal computer based VLSI design curriculum

    Publication Year: 1995, Page(s):250 - 253
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    We have developed a VLSI curriculum based on personal computers that can be used at teaching institutions and corporations alike. The curriculum consists of three courses: a capstone VLSI course, an analog design course, and an advanced digital design synthesis course. No workstations are necessary, laboratories may be given without teaching assistants, and the entire system be used with minimal r... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast algorithm for performance-oriented Steiner routing

    Publication Year: 1995, Page(s):198 - 203
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We present a routing algorithm which minimizes the Elmore delay to the identified critical sinks while producing routes comparable to the best previously existing Steiner router. Since performance oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. Our algorithm has a ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A systolic algorithm and architecture for image thinning

    Publication Year: 1995, Page(s):138 - 143
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    In this paper, we describe a new special purpose VLSI architecture for image thinning. The architecture is systolic and is based on an algorithm that achieves a high degree of parallelism. The proposed algorithm computes the skeleton of multiple objects in an image in linear time by making 2 scans over the 4-distance transform of the image. The algorithm is mapped onto a linear systolic array of s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linking fabrication and parametric testing to VLSI design courses

    Publication Year: 1995, Page(s):246 - 249
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The actual versus simulated performance of VLSI systems is dependent on the accuracy of the simulation model parameters and the soundness of the design rules used. Future process engineers must be schooled in VLSI design principles, while at the same time understanding the origin of the process based design rules and the statistical variation of device model parameters. This paper describes RIT's ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudo-random behavioral ATPG

    Publication Year: 1995, Page(s):192 - 195
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    This paper deals with a new approach for the Automatic Test Pattern Generation (ATPG) of circuits described from a behavioral point of view in VHDL. This approach is based on a pseudo-random process characterized by the fact that criteria for computing the test length and evaluating the quality of the generated data come from the field of software engineering. This paper presents the bases of this... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling of communication protocols in VHDL

    Publication Year: 1995, Page(s):168 - 171
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. In this paper, the feasibility of using VHDL language to model communication protocols is examined, and a modeling methodology for such systems using VHDL is presented. We demonstrate our methodology on the transport protocol ISO/CCITT class... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient building block layout methodology for compact placement

    Publication Year: 1995, Page(s):118 - 123
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In this paper, a new efficient methodology for building block layout is presented by using synthesis placement and compaction. The synthesis placement part of the methodology is based on a formal language called GEOMETRIA. The compaction part is based on geometric reshapings (gs) of blocks and the merging of the communication channels. Both reshaping and merging follow the VLSI regulations for leg... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bus minimization and scheduling of multi-chip systems

    Publication Year: 1995, Page(s):40 - 45
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new approach for modeling and optimization of analog systems

    Publication Year: 1995, Page(s):28 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    This paper introduces a new method to simplify the modeling and optimization of complex analog systems. A matrix is developed to simplify the evaluation of coefficients of the recurrent procedure to model complex analog systems. The authors demonstrate that diverse systems are more accurately modeled compare with bilinear approximation and the technique requires much less computation than traditio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scan testing of asynchronous sequential circuits

    Publication Year: 1995, Page(s):224 - 229
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC unde... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal technology mapping for single output cells

    Publication Year: 1995, Page(s):14 - 19
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    This paper presents a new approach to technology mapping for arbitrary technologies with single output cells. It overcomes the restrictions of tree-mapping based methods. Optimal algorithms for special cases of DAG-mapping are presented: for minimum delay mapping and for duplication-free mapping under a class of simple cost functions (including area and delay). Heuristics for duplication of logic ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A universal formalization of the effects of threshold voltages for discrete switch-level circuit models

    Publication Year: 1995, Page(s):266 - 271
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In most discrete switch-level circuit models, switches, or transistors, are assumed to be perfect. That is, the effects of threshold voltages on signals are neglected in the discrete description of circuit behavior. In the formalization presented in this paper, the effects of imperfection of switches can be calculated separately from the abstracted circuit behavior. Furthermore, this formalization... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel hierarchical global routing for general cell layout

    Publication Year: 1995, Page(s):212 - 215
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Priority driven channel pin assignment

    Publication Year: 1995, Page(s):132 - 135
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    We present a polynomial time improvement of the linear channel pin assignment LCPA algorithms presented by Cai and Wong in 1990. We solve the LCPA problem according to minimum channel density under a special priority schedule subject to vertical constraints and flux. The priority driven linear channel pin assignment algorithm (PDCPA) reduces the channel height by an average of 17% without increasi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimizing wiring space in slicing floorplans

    Publication Year: 1995, Page(s):54 - 57
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    This paper addresses the problem of minimizing wiring space in an existing slicing floorplan. Wiring space is measured in terms of net density, and the existing floorplan is adjusted only by interchanging sibling rectangles and by mirroring circuit modules. An exact branch and bound algorithm and a heuristic are given for this problem. Experiments show that both algorithms are effective in reducin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test

    Publication Year: 1995, Page(s):242 - 245
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The XC4000 Logic Cell Array Family of field programmable gate arrays developed by Xilinx includes support for the IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. Boundary-scan with built-in self-test is known to provide tests of high quality. The design and implementation of boundary-scan with built-in self-test that conforms fully to the IEEE Standard 1149.1 for the XC4000 d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Coding a terminated bus for low power

    Publication Year: 1995, Page(s):70 - 73
    Cited by:  Papers (30)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Coding was proposed as a general method of decreasing power dissipation for the I/O. Lower power dissipation can be obtained by using extra bus liner for coding the data. This paper presents an application of the general theory of limited-weight codes for a class of parallel terminated buses with pull-up terminators (e.g. Rambus). Power dissipation on such a bus-line is larger for a logical 1 and ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test application time reduction for scan based sequential circuits

    Publication Year: 1995, Page(s):188 - 191
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-ato... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Technology mapping algorithms for sequential circuits using look-up table based FPGAS

    Publication Year: 1995, Page(s):164 - 167
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper presents a set of algorithms for mapping sequential circuits onto look-up table based FPGAs and explores how it is possible to reduce the time delay and simplify the final routing results of this mapping. We define several new terms which are used to describe the problem. This work focuses on the mapping of flip-flops and their adjacent combinational parts in sequential circuits using L... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions

    Publication Year: 1995, Page(s):112 - 116
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The use of symbolic techniques to store integer-valued functions has been shown to be extremely effective in handling both transform matrices and spectral representations of large Boolean functions. In this paper we propose a novel application of symbolic Rademacher-Walsh spectral transforms to the evaluation of Boolean function correlation. In particular, we present an ADD-based algorithm to comp... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Uniform area timing-driven circuit implementation

    Publication Year: 1995, Page(s):2 - 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    We consider the problem of selecting the proper implementation of each circuit module from a cell library to minimize the propagation delay along every path from any primary input to any primary output. An earlier problem definition, known as the general circuit implementation problem, assumes that each implementation has different delays on the input-output paths in the circuit, and that differen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A scalable shared buffer ATM switch architecture

    Publication Year: 1995, Page(s):256 - 261
    Cited by:  Papers (2)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A scalable shared buffer switch architecture for asynchronous transfer mode (ATM) with O(√N) complexity for memory bandwidth requirement and maximum crosspoint switch size, and O(N) scalability for buffer memory size is proposed. Access time to buffer memories has been reduced by virtue of parallel access. The switch architecture features multiple buffer memories between the input and output... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing

    Publication Year: 1995, Page(s):204 - 207
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Locally optimal breaking strategy was already developed for disjoint directed circuits in the vertical constraint graph. The paper reports extensions to two classes of nondisjoint circuits: with a common vertex, and with a common path. The significance of this is that the demonstration of general applicability of the locally optimal breaking concept opens a new approach to improving the channel ro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.