[1992] Proceedings International Conference on Wafer Scale Integration

22-24 Jan. 1992

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Displaying Results 1 - 25 of 41
  • Keynote address: critical issues in wafer scale design

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (15 KB)

    Summary form only given. The author discusses critical barriers to the further developments of wafer-scale design technology and its successful transfer to industry. These include: 1) difficulty in obtaining multireticle stepper lithography for sub 2-micron fabrication, (2) limitation to two levels of metal and resulting problems in power and clock distribution, (3) excessive turnaround time becau... View full abstract»

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  • The impact of the declining cost per MIPS

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (12 KB)

    Summary form only given, as follows. The personal computer (PC) cost per million instructions per second (MIPS) is projected to decline to less than $100.00 per MIPS by 1995, and to a few dollars per MIPS by 2010. This cost reduction will be achieved through very large scale integration, multi-chip modules, and operating voltage reduction. Cheap computing power will allow many problems currently h... View full abstract»

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  • Proceedings. International Conference on Wafer Scale Integration (Cat. No.92CH3088-2)

    Publication Year: 1992
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    Freely Available from IEEE
  • Lithographic manufacturing techniques for wafer scale integration

    Publication Year: 1992, Page(s):4 - 13
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A methodology utilizing a mix-and-match approach of optical 1×lithography and e-beam lithography currently used at TRW for WSI (wafer scale integration) technologies is discussed. Field stitching techniques, design considerations, and macrocell grouping techniques which enhance field stitching capability and impact design rules are described for this mix and match e-beam and 1×optical ... View full abstract»

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  • Efficient fault diagnosis of switches in wafer arrays

    Publication Year: 1992, Page(s):341 - 351
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Considers an abstract model of a wafer-scale system where functional modules are connected by connections which run over wiring channels. Programmable switches are located at the junction of these wiring channels. The proposed technique is based on recursively finding progressive fault-free paths across regions of the wafer whose boundaries have been diagnosed to be fault-free. It is shown that su... View full abstract»

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  • An enhanced one-step C-testable design of two-dimensional iterative logic arrays

    Publication Year: 1992, Page(s):331 - 340
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The authors present an improved approach to one-step C-testability of orthogonal two-dimensional iterative logic arrays. This is an improvement of the approach of W. Huang and F. Lombardi (1988) and H. Elhuni et al. (1986). A group of sufficient conditions to test two-dimensional iterative logic arrays with a constant number of test vectors independent of the array size (C-testability) is stated. ... View full abstract»

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  • DFGs for synthesis of alternative architectures: Node activation synthesis

    Publication Year: 1992, Page(s):261 - 270
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    High-level synthesis systems are becoming one of the necessary standards in digital design of complex architectures since they allow a high degree of freedom to the designers in exploring and evaluating architectural alternatives. This possibility is particularly interesting when complex VLSI/WSI (wafer scale integration) architectures are considered. Synthesis and evaluation of alternative archit... View full abstract»

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  • Reconfiguration of two-dimensional VLSI arrays by time-redundancy

    Publication Year: 1992, Page(s):210 - 219
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The authors present various approaches for reconfiguring two-dimensional VLSI arrays using pure time-redundancy, i.e., no spare cells are employed. This technique is based on the full processing utilization of fault free cells. The basic principles of the proposed time-redundancy technique are discussed. The first approach is based on a distributed execution of the reconfiguration process. The sec... View full abstract»

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  • A 3-D WASP module for real-time signal and data processing

    Publication Year: 1992, Page(s):95 - 104
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    Progress to data has concentrated on the integration of 8192 processors on a single silicon wafer (viz., a 2-D WASP (Wafer Scale Integration Associative String Processor) device). The author considers the migration of the design concept to 3-D WASP wafer stacks. A 3-D WASP architecture is described and compared with its 2-D WASP predecessor. Benefits in size, weight, power, reliability, and cost a... View full abstract»

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  • Critical area analysis

    Publication Year: 1992, Page(s):281 - 290
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The critical area is the region on an integrated circuit where the occurrence of a catastrophic spot defect will cause a functional circuit fault. The author describes how to efficiently compute detailed critical areas with the VLASIC Monte Carlo yield simulator. Methods for reducing the computational cost are described, along with some application examples. An SRAM cell failure caused by an extra... View full abstract»

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  • A wafer scale dynamic thermal scene generator

    Publication Year: 1992, Page(s):300 - 309
    Cited by:  Papers (6)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    As a prototype WSTA (wafer scale transducer array), a wafer scale dynamic thermal scene generator is being developed to generate a controllable infrared (IR) image for use in calibrating IR detector arrays. The basic array consists of two cell types, one being a thermal pixel containing a poly Si resistor sitting on a suspended oxide bridge. The second cell contains the addressing, intensity regis... View full abstract»

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  • On self-testing of array systems

    Publication Year: 1992, Page(s):321 - 330
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A novel self-testing method which is applicable to one- and two-dimensional arrays is presented. This method is based on a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifier for PI testability does ... View full abstract»

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  • Design and evaluation of wafer scale clock distribution

    Publication Year: 1992, Page(s):168 - 175
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors describe a computer program which is used for simulating the performance of large wafer scale integration clock distribution networks, made up of both passive transmission line elements and active buffers. The theoretical basis for the model is briefly reviewed. The authors present several example networks for 4-in wafers, comparing the AC performances as a function of power dissipatio... View full abstract»

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  • A WSI rapid prototyping architecture

    Publication Year: 1992, Page(s):35 - 44
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Describes a generalized architecture, the WSI architecture for rapid prototyping (WARP), which attempts to map a large class of algorithms with only two types of processing cells. These are (a) the universal multiply-subtract-add cell (UMSA), and (b) the universal nonlinear cell (UNL). Using these cells, the authors have mapped a radix-8 FFT (fast Fourier transform) algorithm to a wafer architectu... View full abstract»

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  • Optimizing adders for WSI

    Publication Year: 1992, Page(s):251 - 260
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors report on the speed and dynamic power dissipation of CMOS implementations of six different adders. The adders are constructed with inverters and two-to-four-input AND and OR gates. A figure of merit is presented that can be used to compare the adders based on their delay and relative dynamic power consumption. This figure of merit provides a common ground for ranking the adders in term... View full abstract»

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  • Yield optimization of redundant multimegabit RAM's using the center-satellite model

    Publication Year: 1992, Page(s):200 - 209
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Redundant wafer scale memories are analyzed using the center satellite model to determine the optimal redundancy organization for yield enhancement. It is suggested that the degree of redundancy for a memory module be determined depending on its distance from the periphery, as defect density increases as one moves toward the periphery. New analytical expressions for the yield of memory modules wit... View full abstract»

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  • Wideband wafer-scale interconnections in a wafer scale hybrid package for a 1000 MIPS highly pipelined GaAs/AlGaAs HBT RISC

    Publication Year: 1992, Page(s):145 - 154
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    A wideband thin-film wafer scale hybrid package (WSHP) or multi-chip module (MCM) will be used to interconnect the chips of a high-performance RISC (reduced instruction set computer) architecture developed at Rensselaer. This architecture is being implemented using GaAs/AlGaAs heterojunction bipolar transistors (HBTs) and triple-level differential current-mode logic. Because of high power consumpt... View full abstract»

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  • Fault tolerant tree using adaptive operational redundancy

    Publication Year: 1992, Page(s):85 - 94
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The authors describe the architecture of fault-tolerant trees. This fault tolerant architecture is based on a majority decision of redundant operations. It shows that low-area redundancy and dynamic fault recovery are possible. This fault tolerant architecture is suitable for binary trees. Two basic types of fault tolerant architecture are presented: clustered architecture by a node-oriented appro... View full abstract»

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  • SuperChip packaging issues for advanced signal processors

    Publication Year: 1992, Page(s):14 - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    TRW is developing a miniaturized microelectronic, high-performance vector signal processor (VSP) for use in next-generation spaceborne processors and computer workstations. The VSP consists of a monolithic very-high-speed integrated circuit (VHSIC) wafer scale device, the CPUAX (Central Processing Unit Arithmetic eXtended) SuperChip, and two very complex multichip modules, the Control Memory and t... View full abstract»

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  • Optimal group diagnosis procedures for VLSI/WSI array architectures

    Publication Year: 1992, Page(s):352 - 361
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Addresses the problem of partitioning VLSI/WSI (wafer scale integration) array architectures into disjoint maximal diagnosis blocks (MDBs) and finding an optical group diagnosis policy for testing and locating faulty elements (modules) in these MDBs. The optimization criterion is to minimize the accumulated diagnosis cost in deriving a feasible reconfiguration solution. The technique for partition... View full abstract»

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  • High-level design of algorithm-driven architectures: The testability and diagnosability issue

    Publication Year: 1992, Page(s):271 - 280
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Testability and diagnosability represent a mandatory step to be evaluated in the design of complex WSI (wafer scale integration) architectures before restructuring of the architecture to overcome defects can be performed. The authors propose a solution to such issues based on the analysis of testability and diagnosability of the data flow graph derived from the algorithm that has to be implemented... View full abstract»

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  • Hierarchical redundancy for orthogonal arrays

    Publication Year: 1992, Page(s):220 - 229
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Hierarchical redundancy using defect-tolerant replacement circuits is proposed for increasing the yield of large-area LSIs (WSIs) with mesh-connected array structures. The defect-tolerant replacement circuits can be constructed by using direct-connection paths and distributed switches in basic k-out-of-n redundancy schemes. When the proposed redundancy configurations are applied ... View full abstract»

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  • WASP 3: A real time signal and data processor

    Publication Year: 1992, Page(s):105 - 114
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The WASP (WSI Associative String Processor) project is aimed at the production of embedded wafer-scale MPC (massively parallel computer) components, with performance, size, weight, power dissipation, and reliability parameters that are far superior to those obtained using conventional technology. WASP 3 heralds the progression to the WASP experimental program into its application demonstrator phas... View full abstract»

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  • RF-wafer scale integration: a new approach to active phased arrays

    Publication Year: 1992, Page(s):291 - 299
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Describe a recently completed Westinghouse /DARPA effort in which many T/R (transmitter/receiver) modules are fabricated simultaneously on a single 3-inch GaAs wafer. Redundancy in circuit elements is utilized to obtain high yield. The resulting wafer of GaAs T/R cells is utilized as a layer within a more complex package that includes the individual radiating element. The authors update the progre... View full abstract»

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  • Bit serial fault tolerant architectures for convolution and polynomial evaluation

    Publication Year: 1992, Page(s):310 - 319
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    The authors present three distinct serial-input serial-output architectures: two for the computation of discrete convolution (bit-sliced and polyphase convolvers) and one for polynomial evaluation (polynomiers). These devices operate in serial fixed point natural arithmetic. All architectures are characterized by a bit-sliced structure that makes possible easy design and testing. The regular, unif... View full abstract»

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