33rd Design Automation Conference Proceedings, 1996

3-7 June 1996

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  • Proceedings of 33rd Design Automation Conference

    Publication Year: 1996
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    Freely Available from IEEE
  • Tutorial: design of a logic synthesis system

    Publication Year: 1996, Page(s):191 - 196
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (723 KB)

    Logic synthesis systems are complex systems and algorithmic research in synthesis has become highly specialized. This creates a gap where it is often not clear how an advance in a particular algorithm translates into a better synthesis system. This tutorial starts by describing a set of constraints which synthesis algorithms must satisfy to be useful. A small set of established techniques are revi... View full abstract»

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  • A new hybrid methodology for power estimation

    Publication Year: 1996, Page(s):439 - 444
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (787 KB)

    We propose a hybrid approach for estimating the switching activities of the internal nodes in logic circuits. The new approach combines the advantages of the simulation-based techniques and the probability-based techniques. We use the user-specified control sequence for simulation and treat the weakly correlated data inputs using the probabilistic model. The new approach, on one hand, is more accu... View full abstract»

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  • Conference Author/ Panelist Index

    Publication Year: 1996
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    Freely Available from IEEE
  • Design methodology for analog high frequency ICs

    Publication Year: 1996, Page(s):503 - 508
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper presents a methodology suited for high frequency analog IC design. The use of a top-down method with AHDL for circuit designers is proposed. In order to accelerate the re-use of circuits that were previously designed and validated in other ICs, the authors developed a system that eases the re-use in the top-down design environment. Moreover, a model parameter generation technique for bi... View full abstract»

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  • Design methodologies for consumer-use video signal processing LSIs

    Publication Year: 1996, Page(s):497 - 502
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    This paper describes the methodologies used to design a Hi-Vision MUSE decoder for Japanese HDTV and codec LSIs for digital VCRs. Since a large amount of input video data is needed to verify the algorithms and logic designs, reducing the verification time is a key issue in designing these LSIs. We describe the methodology used to verify the video signal processing algorithm and that of the physica... View full abstract»

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  • An exact algorithm for low power library-specific gate re-sizing

    Publication Year: 1996, Page(s):783 - 788
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    In this paper we examine the problem of reducing the power consumption of a technology mapped circuit under timing constraints. Consider a cell library that contains multiple implementations (cells) of the same Boolean function. We first present an exact algorithm for the problem when a complete library is given in a complete library, “all” implementations of each cell are present. We ... View full abstract»

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  • VLSI design and system level verification for the Mini-Disc

    Publication Year: 1996, Page(s):491 - 496
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    In this paper, a new method for the design of complex multimedia ASIC is introduced. Using this design method, VLSI with embedded software and high-speed emulators can be developed concurrently. The method has proven to be effective through actual design of VLSI for audio compression and decompression in a Mini-Disc system View full abstract»

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  • A description language for design process management

    Publication Year: 1996, Page(s):175 - 180
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    A language for defining design discipline characteristics is proposed. Design discipline characteristics such as abstraction levels, design object classifications and decompositions, design objectives, and design methodologies can be defined in a simple machine and human readable form. The language, DDDL, has led to the development of a user interface for Minerva II, a design process management to... View full abstract»

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  • New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

    Publication Year: 1996, Page(s):395 - 400
    Cited by:  Papers (55)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay trade-off curve. We achieve this goal by limiting the solution space to the set of topologies induced by a permutation on the sinks of the net. This constraint allows efficient... View full abstract»

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  • VHDL development system and coding standard

    Publication Year: 1996, Page(s):777 - 782
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1292 KB)

    With the growing complexity of todays ASICs and the number of designers involved in one VHDL ASIC project, the need for a VHDL development system together with coding rules for simulation and synthesis has emerged. This paper describes the VHDL Coding Standard which has been established and the VHDL development system including code entry, code formatting, code compliance checkers, data management... View full abstract»

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  • Optimal wire-sizing formula under the Elmore delay model

    Publication Year: 1996, Page(s):487 - 490
    Cited by:  Papers (49)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be the width of the wire at position x, O⩽x⩽L. We show that the optimal wire-sizing function that minimizes the El more delay through the wire as f(x)=ae-bx , where a>0 and b>0 are constants that can be computed an O(1) time. In the case where lower bound (L>0) and upper bound... View full abstract»

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  • On solving covering problems [logic synthesis]

    Publication Year: 1996, Page(s):197 - 202
    Cited by:  Papers (4)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The set covering problem and the minimum cost assignment problem (respectively known as unate and binate covering problem) arise throughout the logic synthesis flow. This paper investigates the complexity and approximation ratio of two lower bound computation algorithms from both a theoretical and practical point of view. It also presents a new pruning technique that takes advantage of the partiti... View full abstract»

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  • A sparse image method for BEM capacitance extraction

    Publication Year: 1996, Page(s):357 - 362
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Boundary element methods (BEM) are often used for complex 3D capacitance extraction because of their efficiency, ease of data preparation, and automatic handling of open regions. BEM capacitance extraction, however, yields a dense set of linear equations that makes solving via direct matrix methods such as Gaussian elimination prohibitive for large problem sizes. Although iterative, multipole-acce... View full abstract»

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  • Efficient communication in a design environment

    Publication Year: 1996, Page(s):169 - 174
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    This paper presents a new communication service. The novelty of the work resides in the distributed architecture adopted which is based on communication agents in every tool and in every host of the design environment. The importance of the work is demonstrated by the results achieved: improved performance, reduced network traffic and fault-tolerance to host and network failures View full abstract»

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  • Sizing of clock distribution networks for high performance CPU chips

    Publication Year: 1996, Page(s):389 - 394
    Cited by:  Papers (29)  |  Patents (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    In a high performance microprocessor such as Digital's 30O MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a complex grid with multiple drivers. The large capacitance of this distribution grid together with the high clock frequency results in substantial power dissipation in the chip. In this paper, we describe techniques to size the ... View full abstract»

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  • VHDL and Verilog compared and contrasted-plus modeled example written in VHDL, Verilog and C

    Publication Year: 1996, Page(s):771 - 776
    Cited by:  Papers (5)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    This tutorial is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the greatest common divisor (GCD) of two numbers. The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RT... View full abstract»

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  • Efficient approximation algorithms for floorplan area minimization

    Publication Year: 1996, Page(s):483 - 486
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Approximation has been shown to be an effective method for reducing the time and space costs of solving various floorplan area minimization problems. In this paper, we present several approximation techniques for solving floorplan area minimization problems. These new techniques enable us to reduce both the time and space complexities of the previously best known approximation algorithms by more t... View full abstract»

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  • The automatic generation of functional test vectors for Rambus designs

    Publication Year: 1996, Page(s):415 - 420
    Cited by:  Papers (7)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    We present a method for the automatic generation of test vectors for functional verification, giving the advantages of random and directed testing. We show the use of a formal specification as input to a test generator. We present techniques for the efficient implementation of the generator. We discuss our experience with this method applied to commercial designs. We show how our approach is a ste... View full abstract»

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  • Electromigration reliability enhancement via bus activity distribution

    Publication Year: 1996, Page(s):353 - 356
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data flow graph (CDFG) representation of the application onto the buses in the microarchitecture... View full abstract»

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  • Improving the efficiency of power simulators by input vector compaction

    Publication Year: 1996, Page(s):165 - 168
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input vector set must be used which leads to very long simulation time. One solution is to generate a compact vector set that is representative of the original input vector set and can be simulated in a reasonable time. We pro... View full abstract»

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  • Energy characterization based on clustering

    Publication Year: 1996, Page(s):702 - 707
    Cited by:  Papers (36)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    We illustrate a new method to characterize the energy dissipation of circuits by collapsing closely related input transition vectors and energy patterns into capacitive coefficients. Energy characterization needs to be done only once for each module (ALU, multiplier etc.) in order to build a library of these capacitive coefficients. A direct high-level energy simulator or profiler can then use the... View full abstract»

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  • Useful-skew clock routing with gate sizing for low power design

    Publication Year: 1996, Page(s):383 - 388
    Cited by:  Papers (20)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skew may allow a larger timing budget for gate sizing. We construct a useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative a... View full abstract»

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  • Glitch analysis and reduction in register transfer level power optimization

    Publication Year: 1996, Page(s):331 - 336
    Cited by:  Papers (21)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    We present design-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the control and data path parts of the circuit. Based on the analysis, we develop techniques that attempt to reduce glitching power consumption by minimizing generation and propagation of glitches in the RTL circuit. Our techniques... View full abstract»

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  • Integrating formal verification methods with a conventional project design flow

    Publication Year: 1996, Page(s):666 - 671
    Cited by:  Papers (5)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional project design flow. The methodology has been used successfully to verify the protocols within a distributed shared memory machine. We consider the following to be the four main benefits to using the model checker. First, ... View full abstract»

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