[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

14-16 Oct. 1991

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Displaying Results 1 - 25 of 129
  • How to design a parallel computer

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (18 KB)

    Summary form only given, as follows. Computer designers of the 1990s will be able to exploit many years of research into the design of parallel computers. The demands of embedded processing, general purpose computing and supercomputing in the 1990s are far beyond the capabilities of sequential computers. Component designers will use VLSI to produce supercomponents for processing, memory and interc... View full abstract»

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  • Neural networks update

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (18 KB)

    Summary form only given, as follows. Neural networks have been intensively studied as a discipline in their own right in the last five years (late 1980s, early 1990s). Initial claims were extremely ambitious; by using the brain's computing principles, networks would eliminate programming, revolutionize computer architecture and sensor interfacing, make analog VLSI a reality, and give guidance to a... View full abstract»

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  • Design and test-the two sides of a coin

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB)

    Summary form only given. The automation of the design and test of VLSI circuits is discussed. Principles that the author believes will guide the design and test methodology of the future are stated. They are: the principle of hierarchy, the principle of orthogonality, the principle of standardization, and computing resource sharing. The principles apply equally to design and test, strengthening th... View full abstract»

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  • Gigascale integration (GIS) in the 21st century

    Publication Year: 1991
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (35 KB)

    Summary form only given. Opportunities for incorporation of more than one billion transistors and associated interconnections with a single silicon chip or for gigascale integration (GSI) are governed by a hierarchy of limits whose levels can be codified as fundamental, material, device, circuit, and system. Each level of this hierarchy includes both theoretical and practical limits. Theoretical l... View full abstract»

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  • IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (389 KB)
    Freely Available from IEEE
  • Early performance estimation of super scalar machine models

    Publication Year: 1991, Page(s):388 - 392
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs View full abstract»

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  • Fault tolerant VLSI design with functional block redundancy

    Publication Year: 1991, Page(s):432 - 436
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Functional block redundancy is a dynamic redundancy technique for fault tolerance of VLSI circuits with nonregular logic structure, such as gate array designs. It exploits functional similarity of subcircuits, such as repeatedly used counter and shift register functions, to reduce the overhead of standby modules. The example of a manually optimized industrial gate array shows an extremely low over... View full abstract»

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  • Amdahl chip delay test system

    Publication Year: 1991, Page(s):200 - 205
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    The design and implementation of an automatic chip delay test system (CDTS) are described. CDTS has been in use at Amdahl Corporation for over a year and has generated delay tests for about 180 designs ranging from 1000 to 30000 gates, achieving high fault coverage. These designs contain sequential logic and memory elements like random access memories (RAMs). CDTS uses a new scheme for applying de... View full abstract»

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  • On the manifestation of faults to errors in signature analysis

    Publication Year: 1991, Page(s):360 - 363
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The study of the relation between faults and its syndromes in the signature analysis of computer hardware testing is presented. When an incorrect signature is observed, it is caused by one of many possible error sequences that contains errors at different locations. The characteristics of the error distributions are identified for greater fault coverage. Formal analysis is presented in conjunction... View full abstract»

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  • Object caching for performance in object-oriented systems

    Publication Year: 1991, Page(s):379 - 385
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Object-oriented systems exhibit a very high rate of object creation, but most objects are short-lived. As a result, memory-management overhead is significant. An application-specific coprocessor architecture to speed up object creation and memory reclamation in object-oriented systems is described. The architecture supports a bit-vector approach to dynamic storage allocation and liberation. Novel ... View full abstract»

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  • Logic synthesis of 100-percent testable logic networks

    Publication Year: 1991, Page(s):428 - 431
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An approach is presented for the synthesis of 100% testable logic networks based on a test pattern generation system for the identification of redundant faults. A redundancy removal procedure for the elimination of redundant nodes and gates from the network is also presented. Elimination of redundancy is an important task in a logic synthesis system that aims at the synthesis of 100% testable logi... View full abstract»

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  • Synthesis of asynchronous state machines using a local clock

    Publication Year: 1991, Page(s):192 - 197
    Cited by:  Papers (51)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    A novel, correct design methodology for asynchronous state-machine controllers is presented. The goal of this work is a design style as close to a synchronous one as possible, but with the advantages of an asynchronous method. The implementations realize asynchronous state-machine specifications using standard combinational logic, flow latches as storage elements, and a locally-generated clocking ... View full abstract»

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  • Reduced Hamming count and its aliasing probability

    Publication Year: 1991, Page(s):356 - 359
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Hardware overhead reduction through counter selection is considered for the Hamming count compaction test. A method to choose the most effective syndrome and input variable counter pair is given. Both simulation and theoretical analysis illustrate that this method produces an optimal pairing. The aliasing probability of this two-counter test is developed and shown to reduce the exhaustive ones cou... View full abstract»

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  • A fast division algorithm for VLSI

    Publication Year: 1991, Page(s):560 - 563
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A novel and fast method for VLSI division is presented. The method is based on Svoboda's algorithm and uses the radix-2 signed-digit number system to give a divider in which quotient bit selection is a function of the two most significant digits of the current partial remainder. An n-bit divider produces an n-bit quotient in redundant form in 3n gate delays using n View full abstract»

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  • Synthesizing converters between finite state protocols

    Publication Year: 1991, Page(s):410 - 413
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    A general approach for synthesizing inter-process communication devices by adapting labeled transition systems is proposed. An approach is also proposed to generate the finite state machine representing the protocol converter. It is assumed that the data path of the protocol converter is already given. The approach is illustrated by generating the communication process between a four phase master ... View full abstract»

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  • Performance-driven global routing for cell based ICs

    Publication Year: 1991, Page(s):170 - 173
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Advances in VLSI technology and the increased complexity of circuit designs cause performance to become an increasingly important constraint for layout. The issue of delay optimization during the global routing phase is addressed. This problem is formulated as the construction of a bounded-radius spanning tree for a given pointset in the plane, and a family of effective heuristics is presented. Th... View full abstract»

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  • VLSI design automation for the application system/400

    Publication Year: 1991, Page(s):444 - 447
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The VLSI design automation process for the IBM AS/400 is highly focused on the dual goals of short design time and exhaustive verification. Some of the recent developments in the process areas of high level language and synthesis, timing analysis and verification, chip physical design, and system testing are described. The process continues to evolve to meet the dual challenges of shorter design t... View full abstract»

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  • An efficient pattern match architecture for production systems using content-addressable memory

    Publication Year: 1991, Page(s):374 - 378
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A novel and efficient content-addressable pattern match architecture (CAPMA) is proposed to speed up the execution time of the match process of a production system. CAPMA compiles the left-hand side (LHS) of each production into an efficient symbolic form, and creates an effective symbolic accessing mechanism based on a two-level content-addressable memory (CAM) structure for computing the conflic... View full abstract»

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  • Random testability of redundant circuits

    Publication Year: 1991, Page(s):424 - 427
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    It is shown that the common belief that any optimized, i.e., nonredundant, circuit is easier to test than its nonoptimized counterpart is not fully justified. It is demonstrated by example that a redundant circuit may be more suitable for random testing than its optimized counterpart. A rule which specifies when redundancy is likely to enhance random testability of a two-level AND-OR gate network ... View full abstract»

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  • Self-timed logic using current-sensing completion detection (CSCD)

    Publication Year: 1991, Page(s):187 - 191
    Cited by:  Papers (19)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A completion-detection method is proposed for efficiently implementing Boolean functions as self-timed logic structures. Current-sensing completion detection (CSCD) allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encodi... View full abstract»

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  • The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order

    Publication Year: 1991, Page(s):524 - 527
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Channel graphs for nonsliceable floorplans are studied for determination of feasible channel routing order. The minimum feedback vertex set (MFVS) formulation is revisited and a polynomial time heuristic is presented. It is shown that feasible routing orders with reserved channels, L-channels, and monotone channels can be obtained from a given MFVS for any floorplan. This approach provides a power... View full abstract»

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  • Incremental synthesis for engineering changes

    Publication Year: 1991, Page(s):40 - 43
    Cited by:  Papers (26)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The problem of rectifying design incorrectness due to specification changes as well as design errors of VLSI circuits is formulated and a basic approach using logic synthesis techniques is presented. An efficient approach is presented for rectifying the functional incorrectness by attaching circuitry exterior to the original design. A necessary and sufficient condition for full rectification of th... View full abstract»

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  • Logic design for a high performance mainframe computer-the HITAC M-880 processor

    Publication Year: 1991, Page(s):14 - 20
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Logic design and its effects on the HITAC M-880 basic scalar processor are described. The M-880 is a high end mainframe computer which uses current high speed circuits and packaging technologies, as well as logic methods, to improve performance. An optimal pipeline stage evaluation method is proposed, together with a new cache access method termed merge access. The combined effect of the logic met... View full abstract»

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  • Aliasing probability in multiple input linear signature automata for q-ary symmetric errors

    Publication Year: 1991, Page(s):352 - 355
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The aliasing probability in single and multiple input linear automata signature registers (LASRs: linear feedback shift registers (LFSRs) and linear cellular automata) has been widely studied under the independent bit error model. Aliasing in a class of multiple-input LASRs (MILASRs) under the q-ary symmetric error model is examined. By modeling the signature analyzer as a two state Marko... View full abstract»

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  • New implementations, tools, and experiments for decreasing self-checking PLAs area overhead

    Publication Year: 1991, Page(s):275 - 281
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is that they involve a significant increasing of the circuit area. Recent experiments on Berger code encoded programmable logic arrays (PLAs) result in 46.9% average area overhead. In order to decrease this overhead, some other self-checking PLA implementations ... View full abstract»

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