Proceedings ED&TC European Design and Test Conference

11-14 March 1996

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  • Proceedings of European Design and Test Conference

    Publication Year: 1996
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    Freely Available from IEEE
  • Silicon technology: risks, opportunities, and challenges

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (113 KB)

    The impressive progress in microelectronics technology over the last two decades has delivered an enormous increase in computational power and storage capacity at ever decreasing cost per function. The general consensus an industry and academia is that this exponential growth in complexity will continze for at least 15 more years. Further progress will require an interdiscaplinary approach compris... View full abstract»

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  • Future of testing: Reintegration of design, testing and manufacturing

    Publication Year: 1996
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (374 KB)

    For at least last 20 years dkroelectronics has been evolving rapidly tracking - almost without a single deviation - Moore's Law. At the beginning of nineteen nineties some level of concern was expressed whether continuing along Moore?????????s prediction makes economic sense. As a response to the above and other concerns in 1993 and 1994 the Semiconductor Industry Association (SIA) has proposed ??... View full abstract»

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  • Addressing the Challenges of System-On-A-Chip Design

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    Summary form only given, as follows. While systems-on-silicon (SOS) products can range from cellular phones to 200-pound avionics communications and navigation systems, they present common problems to the EDA and semiconductor industries. First, SOS applications demand very high levels of integration and functionality, which can only be met through new sub-micron IC technologies. Second, they embr... View full abstract»

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  • The use of microelectronics for future telecom and multimedia systems

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (46 KB)

    Summary form only given, as follows. As a world-leader in telecommunication and multimedia system developments, Alcatel-Bell will present the main trends and challenges for the coming years for microelectronic system design in these domains. Political objectives stimulate competition today: privatization and liberalization are currently changing the world telecom market. The continuous evolution i... View full abstract»

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  • Perturb and simplify: optimizing circuits with external don't cares

    Publication Year: 1996, Page(s):402 - 406
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (562 KB)

    Earlier optimization techniques based on Automatic Test Pattern Generation could not handle external don't cares. We propose a technique that uses external don't cares during the ATPG guided logic optimization. This technique transforms external don't cares into internal don't cares. Thus, the optimization can utilize the external don't cares to obtain better results. Additionally, we also discuss... View full abstract»

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  • VLSI design of a high speed soft decision Viterbi detector

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Summary form only given. The design of a Viterbi detector for high speed disk drive channels is presented. The detector is a soft decision detector that operates on a time varying trellis based on a matched spectral null code. The design was developed by creating a high-level model of the system to resolve high-level design issues. Standard design tools were used for logic simulation and layout ge... View full abstract»

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  • Formal specification of a reactive system: an exercise in VHDL, LOTOS and UNITY

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (103 KB)

    Summary form only given. We are developing a specification and proof environment, called PREVAIL, which is to support several input languages (currently, only VHDL is supported) and which proposes a set of proof tools to verify appropriate descriptions/specifications. Nqthm is one of these tools, and we are working at defining an induction-based method to validate concurrent systems using this pro... View full abstract»

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  • Generalized Recognition Of Gates: a VLSI abstraction tool

    Publication Year: 1996
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    Summary form only given. The Generalized Recognition Of Gates is an innovative and technology independent tool of abstraction. It translates any VLSI or ASIC microelectronic circuit from its netlist format into both VHDL and VERILOG descriptions which express its behavior. The CMOS, NMOS, bipolar and BiCMOS technologies can all be handled. One of the most important characteristics of the tool is t... View full abstract»

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  • A combined pairing and chaining algorithm for CMOS layout generation

    Publication Year: 1996
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (99 KB)

    Summary form only given. As CMOS VLSI circuits increment, their complexity and specifications become more aggressive, automatic layout generators gain popularity. These tools divide their task into a set of steps that include transistor pairing, chaining, sizing, placement of diffusion strips and routing. In each of these steps a high optimization degree is required in order to achieve good result... View full abstract»

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  • Self-checking and fault tolerant approaches can help BIST fault coverage: a case study

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (109 KB)

    Summary form only given. We describe the design of an FIFO component with BIST capabilities. The component is now being used in the Italtel standard library and is exploited in several industrial designs. Our main contribution is to show how the effectiveness of complex BIST design can be improved, and brought to acceptable fault coverage levels, through the coupling with more advanced test archit... View full abstract»

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  • Applying behavioural level test generation to high-level design validation

    Publication Year: 1996
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (118 KB)

    Summary form only given. The methods for verifying an implementation with respect to the specified behavioural VHDL description are not sufficiently developed yet. Therefore the correct behaviour of the implementation has to be validated by simulation. Since it is impossible to simulate the implementation completely, suitable simulation patterns have to be selected for executing statements, operat... View full abstract»

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  • Design of test modules for the analysis of MCM interconnects

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB)

    Summary form only given. A thin-film Multichip Module (MCM-D) switching unit, specifically designed for performance analysis of interconnection substrates, is described. A test approach is presented for the characterisation of a given device technology as a function of geometrical, physical and electrical quantities-in this particular case, a MCM-D technology and a 0.7 /spl mu/m CMOS technology. View full abstract»

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  • System fault diagnosis based on a fuzzy qualitative approach

    Publication Year: 1996
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (117 KB)

    Summary form only given. A novel automated approach combining structural description and fuzzy logic for both sequential and combinational system fault diagnosis is presented. It does not use any specific fault model. The software implementing this method is described, and some experimental results are provided. View full abstract»

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  • An automated design environment for micromechanical sensors

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (97 KB)

    Summary form only given. In this paper, we present a computer-aided design system for MicroMechanical Sensors (MMS). Moreover, it allows designer to improve automatically MMS response by the means of dimensions or shape modification of their design. Our system has a modular architecture centered around a widespread Finite-Element (FE) code, Ansys. View full abstract»

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  • Methods and tools for the design of electrostatic micromotors

    Publication Year: 1996
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (97 KB)

    Summary form only given. In this paper the methodology of the design of electrostatic micromotors is discussed. Field computation is performed by the finite element method (FEM). Automated modelling and evaluation of the quantities of the electrostatic field in combination with an equivalent circuit technique leads to an efficient design tool. View full abstract»

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  • Author index

    Publication Year: 1996
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    Freely Available from IEEE
  • High rate soft output Viterbi decoder

    Publication Year: 1996, Page(s):315 - 319
    Cited by:  Papers (4)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s, 8 states, R=1/2), using the “radix” trellis method to speed up the rate of a decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Beca... View full abstract»

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  • FPGA synthesis for minimum area, delay and power

    Publication Year: 1996
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    In this paper, we address the problems of minimizing the area, delay and power during synthesis of field programmable gate arrays (FPGAs). We use Boolean decomposition techniques to minimize the number of configurable logic blocks (CLBs), the depth of the network and the power dissipations. We use OBDDs to represent functions so that our methods can be implemented more effectively. Our mapping alg... View full abstract»

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  • VLSI architecture for motion estimation using the block-matching algorithm

    Publication Year: 1996, Page(s):310 - 314
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture, EST256, consists of 256 processor elements, deals with a search area of -8/+7 and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 μm double-metal... View full abstract»

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  • A spectral method for Boolean function matching

    Publication Year: 1996
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    An approach to Boolean matching with respect to NPN operations, i.e. negation of the function, permutation of the inputs and negation of the inputs, is presented. The method is based on a canonical form defined in the Hadamard spectral domain. When applied to technology mapping, the idea is to keep the canonical function with each library cell, and to compute the canonical function for a subcircui... View full abstract»

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  • Exploiting functional dependencies in finite state machine verification

    Publication Year: 1996, Page(s):9 - 14
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    This paper proposes a novel verification method for finite state machines (FSMs), which automatically exploits the relation between the state encodings of the FSMs under consideration. It is based on the detection and utilization of functionally dependent state variables. This significantly extends the ability of the verification method to handle FSMs with similar state encodings. The effectivenes... View full abstract»

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  • An approach for a dynamic generation/validation system for the functional simulation considering timing constraints

    Publication Year: 1996, Page(s):302 - 306
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    This paper presents a method for the automatic validation of the timing behavior of RT and gate level VHDL descriptions. Using a machine-readable timing specification, we automatically create a VHDL testbench for the stimuli generation and the validation of the expected responses. We have developed a VHDL package using linear programming algorithms to compute a valid set of stimuli. The model resp... View full abstract»

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  • Algebraic support for transformational hardware allocation

    Publication Year: 1996
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    Hardware reusability in high-level synthesis is based on the possibility of mapping several operators to the same hardware module. This possibility may dramatically depend on the ability of the design tool to recognize operators that can mapped to a single module. This work presents a uniform framework to formally express the semantics of hardware modules, in order to support transformational hard... View full abstract»

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  • K*BMDs: a new data structure for verification

    Publication Year: 1996, Page(s):2 - 8
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Recently, two new dates structures have been proposed in the area of Computer Aided Design (CAD), i.e. Ordered Kronecker Functional Decision Diagrams (OKFDDs) and Multiplicative Binary Moment Diagrams (*BMDs). OKFDDs are the most general ordered data structure for representing Boolean functions at the bit-level. *BMDs are especially applicable to integer valued functions. In this paper we propose ... View full abstract»

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