Proceedings of the Fourth Asian Test Symposium

23-24 Nov. 1995

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Displaying Results 1 - 25 of 59
  • Fanout fault analysis for digital logic circuits

    Publication Year: 1995, Page(s):33 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (659 KB)

    Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Im... View full abstract»

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  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (94 KB)
    Freely Available from IEEE
  • Testable design of non-scan sequential circuits using extra logic

    Publication Year: 1995, Page(s):176 - 182
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or test... View full abstract»

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  • An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits

    Publication Year: 1995, Page(s):237 - 243
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    An improved hierarchical testing algorithm for combinational circuits with repetitive sub-circuits using the bus fault model has been proposed. This model exploits the regularity of a circuit by grouping together identical gate-level sub-circuits into high-level sub-circuits. Though the existing test generation techniques using this model reduces the required time substantially in many cases, it f... View full abstract»

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  • Test sequence compaction by reduced scan shift and retiming

    Publication Year: 1995, Page(s):169 - 175
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. In this work, retiming, which repositions flip-flops, is introduced to enhance the effect of the reduced scan shift. When the number of flip-flop... View full abstract»

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  • Fast functional testing of delay-insensitive circuits

    Publication Year: 1995, Page(s):375 - 381
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Although the advantages of delay-insensitive and self-timed circuits with respect to speed and operation are known, their advantages in terms of testing are not examined. We focus our attention on testing four-phase handshake signalling based circuits designed using Martin's method. Due to the distributed nature of the control part of a delay-insensitive circuit, it is possible to simultaneously t... View full abstract»

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  • Identification of robust untestable path delay faults

    Publication Year: 1995, Page(s):229 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    This paper presents a theoretical analysis to identify robust untestable path delay faults. It first classifies the path reconvergence of fanouts into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure was applied to ISCAS... View full abstract»

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  • Test configurations to enhance the testability of sequential circuits

    Publication Year: 1995, Page(s):160 - 168
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operat... View full abstract»

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  • A new method for testing mixed analog and digital circuits

    Publication Year: 1995, Page(s):127 - 132
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    In this paper a new method is proposed for observing analog test points inside integrated circuits that enables the simultaneous observation of a large number of points. The method permits the removal of the analog multiplexer from the signal path and a reduction of the load introduced at the observed test points. A charge coupled device analog shift register is used to sample input voltage and sh... View full abstract»

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  • Power supply current detectability of SRAM defects

    Publication Year: 1995, Page(s):367 - 373
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    We investigate correlations between SRAM cell defects and power supply current including IDDQ (peak value of quiescent power supply current) and iDDT (transient power supply current). Our results show that the power supply current can be used to detect cell shorts, cell opens, and disturb-type pattern sensitivity. We also investigate the effect of total current leakage in the... View full abstract»

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  • Static compaction for two-pattern test sets

    Publication Year: 1995, Page(s):222 - 228
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Ex... View full abstract»

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  • Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

    Publication Year: 1995, Page(s):346 - 352
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential... View full abstract»

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  • Unified scan design with scannable memory arrays

    Publication Year: 1995, Page(s):153 - 159
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Scan design has been popular as a design-for-testability technique. A memory array, however, has been considered non-scannable. This paper describes unified scan design that makes a memory array scannable and allows mixing of memory arrays and ordinary flip-flops in a single scan path. Based on a rule that considers ordinary flip-flops as a memory array with one word, the existing CAD system can g... View full abstract»

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  • A simple technique for locating gate-level faults in combinational circuits

    Publication Year: 1995, Page(s):65 - 70
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    This paper presents a simple technique for locating single gate-level faults in combinational circuits. This technique consists of three processes; first, finding possible error sources from the observed errors, second, deducing possible faults from them and finally eliminating faults incapable of being in the circuit under test. Computer simulation was done for ISCAS'85 benchmark circuits to eval... View full abstract»

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  • DC control and observation structures for analog circuits

    Publication Year: 1995, Page(s):120 - 126
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    As the complexity of electronic circuits and systems increases, so does the complexity of testing them. The level-sensitive scan-design (LSSD) structure used in a digital circuit enhances the controllability and observability of the circuit under test. For analog circuits, there also are several approaches proposed to improve their observability, based on the LSSD concept. However, none of these a... View full abstract»

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  • Metastability evaluation method by propagation delay distribution measurement

    Publication Year: 1995, Page(s):40 - 44
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    This paper suggests an experimental method for determining metastability properties based on deliberately inducing metastability in edge-triggered flip-flops. It offers the opportunity to analyze the impact of input signals time relationship on the output signal timing characteristics, using graphical and analytical representation of the propagation delay density distribution function. A new appro... View full abstract»

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  • Testing of a parallel ternary multiplier using I2L logic

    Publication Year: 1995, Page(s):387 - 391
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    A generalized model for faults in multivalued I2L circuits has been proposed. Using this model, the test sets have been generated for testing the basic modules of a parallel multiplier using multivalued I2L technology. These basic modules include four input balanced ternary full adder and a precarry generator, each of which has multivalued current inputs and outputs. The gene... View full abstract»

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  • Low power design and its testability

    Publication Year: 1995, Page(s):361 - 366
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    In this paper, we propose a power reduction tool named PORT, which evaluates the power dissipation factor Φ by utilizing the transition probability, and which reduces Φ by utilizing sets of permissible functions. Experimental results show the usefulness of PORT. Next, we will consider on the testability of circuits transformed by PORT. The size of the test set generated by compact test set... View full abstract»

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  • Overhead reduction techniques for hierarchical fault simulation

    Publication Year: 1995, Page(s):79 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Overhead reduction techniques for hierarchical fault simulation are presented which reduce simulation overhead for the concurrent method and its expanded version, the Multi-List-Traversal method. The techniques include a one-pass fault simulation strategy, characteristic vectors, and contiguous concurrent machines. The cost of each process for the conventional and new methods is formulated for com... View full abstract»

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  • Fast fault simulation for BIST applications

    Publication Year: 1995, Page(s):93 - 99
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propa... View full abstract»

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  • Generator choices for delay test

    Publication Year: 1995, Page(s):214 - 221
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions... View full abstract»

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  • Functional test generation for path delay faults

    Publication Year: 1995, Page(s):339 - 345
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    We present a novel test generation technique for path delay faults, based on the growth (G) and disappearance (D) faults of programmable logic arrays (PLA). The circuit is modeled as a PLA that is prime and irredundant with respect to every output. Certain tests for G faults, generated by using known efficient methods are transformed into tests for path delay faults. Our algorithm generates tests ... View full abstract»

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  • Testability forecasting for sequential circuits

    Publication Year: 1995, Page(s):199 - 205
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Of all the developments of testable as well as reliable designs for computing systems, test generations for sequential circuits are usually viewed as one of the hard nuts to be solved in terms of complexity and time-consumption. Although some dozens of algorithms have been proposed to cope with these issues, much still remains to be desired in solving such problems so as to determine: (1) which of... View full abstract»

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  • Universal test complexity of field-programmable gate arrays

    Publication Year: 1995, Page(s):259 - 265
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random ac... View full abstract»

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  • Theory and applications of cellular automata for synthesis of easily testable combinational logic

    Publication Year: 1995, Page(s):146 - 152
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    Characterization of a special class of nongroup CA termed as D1*CA has been proposed previously (1993) along with its application for synthesis of easily testable FSM. This paper extends application of the D1*CA as an ideal test machine for testing combinational logic (CL) blocks and registers of a circuit. Such a test machine can be conveniently embedded in the data path synthesis phase around th... View full abstract»

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