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[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

26-29 May 1991

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  • Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic (Cat. No.91CH3009-8)

    Publication Year: 1991
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  • A transformation of multiple-valued input two-valued output functions and its application to simplification of exclusive-or sum-of-products expressions

    Publication Year: 1991, Page(s):270 - 279
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    A transformation for p-valued input functions is presented. The number of products in minimum exclusive-or sum-of-products expressions (ESOPs) is invariant under this transformation. Algorithms for reducing the number of product terms in ESOPs using this transformation are presented for p=2 and p =4. Arithmetic functions are simplified to show the ability of this approac... View full abstract»

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  • A note on minimal partial clones

    Publication Year: 1991, Page(s):262 - 267
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Clones of partial operations playing important role in the theory of partial algebras and in computer science are considered. It is shown that the atoms of the lattice LpA of all partial clones are either the atoms of LoA or are generated by partial projections, defined on a totally reflexive and totally symmetric domain View full abstract»

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  • Application of multi-zero artificial neural network to the design of an m-valued digital multiplier

    Publication Year: 1991, Page(s):32 - 37
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    An M-ary digital multiplier using artificial multi-zero neural networks and elementary analog arithmetic units has been derived. This multiplier should be accurate because its main arithmetic process is digital, while the speed should be very high because it is a free-running, parallel, and M-ary operation. The multi-zero neural network is a feedback artificial neural system cons... View full abstract»

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  • Worst case number of terms in symmetric multiple-valued functions

    Publication Year: 1991, Page(s):94 - 101
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    A symmetric multiple-valued function realized as the disjunction of fundamental symmetric functions is addressed. A simpler disjunction can be formed when the latter functions combine in the same way that minterms combine to form simpler product terms for sum-of-products expressions. The authors solve the problem, posed by J.C. Muzio (1990), that sought the worst-case symmetric function in the sen... View full abstract»

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  • On the complexity of enumerations for multiple-valued Kleenean functions and unate functions

    Publication Year: 1991, Page(s):55 - 62
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Multiple-valued Kleenean functions are represented by multiple-valued AND, OR, NOT, variables and constants. In their previous work (see proc. of 20th Int. Symp. Multiple Valued Logic, IEEE, p.410-17, 1990), the authors pointed out that both mapping from Kleenean functions to some (3,p)-functions and mapping from unate functions to some (2,p)-functions are bijections. In this pap... View full abstract»

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  • NPN calculi: a family of three strict Q-algebras

    Publication Year: 1991, Page(s):255 - 261
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    NPN (negative-positive-neutral) calculi, a family of three mathematical structures are introduced for qualitative reasoning. NPN crisp logic extends the usual 4-valued model {+, -, 0, ?) to a 6-valued model {1, 0, +1, (-1, 0), (0, +1), (-1, +1)} and adds one more level of specification to the usual model. NPN fuzzy logic extends the NPN model to the space {∀(x,y)|x View full abstract»

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  • A floating-gate-MOS-based multiple-valued associative memory

    Publication Year: 1991, Page(s):24 - 31
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory info... View full abstract»

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  • Recognition of circle form using fuzzy sequential system

    Publication Year: 1991, Page(s):85 - 92
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    An application of the synchronous fuzzy sequential system to pattern recognition in which fuzzy propositions are used to represent various sizes of circles is presented. The advantages of the proposed system include the small amount of required memory elements as well as a fast recognition speed caused by the sequential procedure. Furthermore, an easy realization of the system with electronic devi... View full abstract»

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  • A comparative study of programmable realization techniques of multi-valued multi-threshold functions

    Publication Year: 1991, Page(s):372 - 381
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    Four programmable structures have been proposed earlier for realization of multivalued multithreshold (MVMT) functions. Each of these structures consists of repeated modules each of which realizes either a unit step function or a staircase function. Two structures for realization of MVMT functions are introduced which are shown to be superior to existing structures in terms of the chip-pin count n... View full abstract»

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  • Testability analysis of CMOS ternary circuits

    Publication Year: 1991, Page(s):158 - 165
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circui... View full abstract»

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  • Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations

    Publication Year: 1991, Page(s):330 - 339
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set {0, 1, 2, 3}. The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a ti... View full abstract»

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  • Improving tableau deductions in multiple-valued logics

    Publication Year: 1991, Page(s):230 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    Path dissolution is an efficient generalization of the method of analytic tableaux. Both methods feature (in the propositional case) strong completeness, the lack of reliance upon conjunctive normal form (CNF), and the ability to produce a list of essential models (satisfying interpretations) of a formula. Dissolution can speed up every step in a tableau deduction in classical logic. The authors c... View full abstract»

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  • A non-commutative multiple-valued logic

    Publication Year: 1991, Page(s):49 - 54
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A set of operations which can be used to design n-valued switching functions is given. These give rise to a class of algebras which are left-handed skew lattices together with dual implication operation. Such algebras form a decidable discriminator variety, and hence possess a well-behaved structure theory and satisfy many identities. Algorithms for the design and optimization of switchin... View full abstract»

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  • On the maximum size of the terms in the realization of symmetric functions

    Publication Year: 1991, Page(s):110 - 117
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The symmetric functions of m-valued logic have a sum-product (i.e. max-min) representation whose terms are sums of fundamental symmetric functions (FSFs). These sums may be simplified if they contain adjacent SFSs. This naturally leads to the combinatorial problem of determining the maximum size M(m,n) of adjacent-free sets of n-variable SFSs. J.C. Muzi... View full abstract»

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  • Theory and uses of Post algebras of order ω+ω*. II

    Publication Year: 1991, Page(s):248 - 254
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    For pt.I see Proc. 20th International Symposium on Multiple- Valued Logic ISMVL 1990 p42-47. The paper is a continuation of the author's previous work that presents a stronger version of post algebras of order ω+ω whose chain of constants is isomorphic with (0⩽1⩽2⩽. . .⩽-3⩽-2⩽-1). The algebras are a generalization of Post algebras of finite order, and... View full abstract»

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  • A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems

    Publication Year: 1991, Page(s):16 - 23
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS trans... View full abstract»

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  • Topological soft algebra for the S5-modal fuzzy logic

    Publication Year: 1991, Page(s):80 - 84
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A topological fuzzy algebra is defined as a special case of topological soft algebra. This algebra system is obtained from the S5-modal fuzzy logic, which had been previously proposed. The soundness and completeness of this axiomatic system are proved View full abstract»

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  • A decade of spectral techniques

    Publication Year: 1991, Page(s):182 - 188
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Some of the significant achievements of the last ten years in the area of spectral techniques are summarized. The name spectral techniques denotes developments in abstract harmonic analysis oriented to possible applications in switching theory and logic design, fault detection, coding theory, and pattern analysis. A review of pattern analysis, with emphasis on the study of self-similarity of patte... View full abstract»

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  • An investigation into the implementation costs of residue and high radix arithmetic

    Publication Year: 1991, Page(s):364 - 371
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Due to the need for coexistence with binary logic, the implementation of multiple-valued logic must deal with the representations that are conceptually multiple-valued, but physically binary. Some theoretical insights about the VLSI implementation based on a programmable logic array (PLA) approach are presented. The study of these output functions reveals an interesting problem domain that paralle... View full abstract»

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  • On the synthesis of 4-valued current mode CMOS circuits

    Publication Year: 1991, Page(s):147 - 155
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    Synthesis of 4-valued current mode CMOS circuits is considered. A method for deriving low-cost realizations of single-variable functions, based on the incremental cost approach, is presented. A technique for synthesis of 2-variable functions, incorporating a modified direct cover approach, is considered. The results show that this technique can be used effectively in conjunction with the multiplex... View full abstract»

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  • Reasoning about digital systems

    Publication Year: 1991, Page(s):2 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The uses of automated reasoning in the process of the design and analysis of digital systems are explored. A discussion of reasoning and automated reasoning is presented. Several examples of successful application of this technology are described, and current research is discussed. The author mentions AURA (automated reasoning assistant), ITP (interactive theorem prover) and flow nets View full abstract»

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  • An algorithm for the solution of multi-valued logic programming

    Publication Year: 1991, Page(s):322 - 327
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Logic programming using the Horn clause in the field of artificial intelligence is considered. It has been previously reported that the solution of multivalued logic programming with many truth values is obtained by solving the multivalued logic formula expressed in the Postian algebra. In this paper, expanding the idea that unnecessary search can be avoided by using an indeterminate value, an alg... View full abstract»

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  • Undecidability in the completion of truth-function logic

    Publication Year: 1991, Page(s):225 - 229
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The inchoate rules of truth of logicism are cohered into the epistemic genesis for mathematics. First the formal truth conditions are exhausted with the complementary indeterminate value, not true and not false. The alternant truth assignments of the determinate Sheffer truth-conferring rules are not exhaustive of the propositional states of affairs necessary for conferring the founding truths. By... View full abstract»

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  • On the maximum number of implicants needed to cover a multiple-valued logic function using window literals

    Publication Year: 1991, Page(s):280 - 286
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Some bounds on the maximum number of implicants needed in a minimal sum of products expression using window literals and the truncated sum, operation are investigated. Functions with one input variable require at most r implicants in their minimum sum of products expression, where r is the radix of the function. Two variable functions with radix less than eight are analyzed. No f... View full abstract»

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