Proceedings of IEEE International Test Conference - (ITC)

17-21 Oct. 1993

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Displaying Results 1 - 25 of 131
  • Multiconfiguration technique to reduce test duration for sequential circuits

    Publication Year: 1993, Page(s):989 - 997
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB)

    Sequential ATPGs, now, are able to handle an appreciable degree of sequentiality, thus allowing to treat partial scan implementations with a suitable fault coverage. Nevertheless, with these methods the test duration remains often prohibitive due to the long scan register. The DFT method we present is based on cycle breaking and sequential depth reduction guided by graph analysis. When a flip-flop... View full abstract»

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  • Known good die for MCMs: Enabling technologies

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (105 KB)

    Summary form only given, as follows. The need for known good die for MCMs has been widely recognized. However, satisfying this need has presented many test challenges. Fortunately, the efforts of many workers are now providing the basic technology to assure the performance and reliability of die to be used in MCMs. Performance testing of ICs and chips on wafers is illustrated at gigahertz rates wi... View full abstract»

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  • Test generation with high coverages for quiescent current test of bridging faults in combinational circuits

    Publication Year: 1993, Page(s):73 - 82
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (879 KB)

    Two test strategies for external and internal shorts in FCMOS combinational circuits, based on current consumption monitoring, are proposed and analysed: (a) pseudorandom test with a small number of vectors, and (b) a new strategy called current testing vector generation based on stuck at Faults (CUTEGENS). Both test strategies have been experimented on a set of combinational benchmark circuits. T... View full abstract»

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  • Proceedings of IEEE International Test Conference - (ITC)

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (36 KB)
    Freely Available from IEEE
  • CHEETA: Composition of hierarchical sequential tests using ATKET

    Publication Year: 1993, Page(s):606 - 615
    Cited by:  Papers (38)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    An approach to modular and hierarchical sequential circuit test generation, which exploits a top-down design methodology, uses high level test knowledge and constraint driven module test generation to target faults at the structural level, is introduced in this paper. Results obtained for several designs are provided to demonstrate the effectiveness of our approach and the need for high level know... View full abstract»

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  • Switch-level ATPG using constraint-guided line justification

    Publication Year: 1993, Page(s):616 - 625
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    This paper explores a test pattern generation problem for switch-level combinational circuits. In test generation for switch-level circuits, constraints on assignable logic values can be introduced due to the difference between the implicated logic values and the justifiable logic values of a logic element. Therefore, identifying unjustifiable logic values as early as possible would greatly accele... View full abstract»

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  • Synthesizing for scan dependence in built-in self-testable designs

    Publication Year: 1993, Page(s):734 - 743
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths such that some of the BIST and scan logic is shared with the functional logic. Logic sharing is possible when scan dependence is introduced in the desig... View full abstract»

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  • Design-for-test techniques utilized in an avionics computer MCM

    Publication Year: 1993, Page(s):373 - 382
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    This paper highlights the development of a multichip module (MCM) design-for-testability methodology for an application intended for use in a fully electronic active matrix LCD flight instrument. MCM test issues discussed include design-for-testability, substrate test, known-good die (KGD), and module level test. The design incorporates IEEE 1149.1 and built-in-self-test features. Bare die pretest... View full abstract»

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  • On the design for testability of communication software

    Publication Year: 1993, Page(s):190 - 199
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    Communication software is an implementation of the communication protocols involved in a distributed system. In this paper we examine the important factors related to protocol design that affect testing and testability of communication software View full abstract»

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  • IDD pulse response testing on analog and digital CMOS circuits

    Publication Year: 1993, Page(s):626 - 634
    Cited by:  Papers (45)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    This paper presents a new method for detecting defect and fabrication variations in both digital and analog CMOS circuits by simultaneously pulsing the power supply rails and analyzing the temporal and/or the spectral characteristics of the resulting transient rail currents. The method presented has a distinct advantage over other forms of iDD testing because it requires a single test v... View full abstract»

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  • Development of a fault model and test algorithms for embedded DRAMs

    Publication Year: 1993, Page(s):815 - 824
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB)

    Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophic and non-catastrophic defects, an accurate and efficient fault model has been developed. Using this... View full abstract»

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  • A conditional resource sharing method for behavioral synthesis of highly testable data paths

    Publication Year: 1993, Page(s):744 - 753
    Cited by:  Papers (16)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    Existing conditional resource sharing methods using in behavioral synthesis focus on area and performance optimization and do not consider testability. This paper extends our previous work to handle conditional branches. A hierarchical control-data flow graph (HCDFG) is used to model the system behavior. A postorder traversal of the HCDFG is employed to reduce sequential depths and loops for testa... View full abstract»

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  • Integrating electrical test into final assembly

    Publication Year: 1993, Page(s):585 - 589
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper describes a set of projects that combine integrated circuit assembly steps. The completed set of projects will allow direct shipment of devices to customers from the end of the trim and form press. The integrated process steps include strip inspection, device mark, mark inspection, dambar removal, lead trim, final test, device form, device singulation, coplanarity inspection, reject sor... View full abstract»

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  • Control and observation of analog nodes in mixed-signal boards

    Publication Year: 1993, Page(s):323 - 331
    Cited by:  Papers (23)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    BST is a well established standard and testability framework for digital ICs and boards. The paper presents a test support IC controlled by an IEEE1149.1 interface, capable of providing access to analog nodes in mixed-signal boards. The proposed architecture (ABSINT - Analog to Boundary Scan Interface) is described and relevant implementation issues are discussed. A demonstrator IC implementing th... View full abstract»

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  • Efficient testing of software modifications

    Publication Year: 1993, Page(s):859 - 864
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    As software products evolve, regression testing is a necessary part of the development process. We present methods to automate and analyze change tracking for requirements and test cases so we may partially automate the process of revising the regression test suite for the modified software, and eliminate the necessity to rerun test cases that are unaffected by the modifications View full abstract»

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  • Delay testing for non-robust untestable circuits

    Publication Year: 1993, Page(s):954 - 961
    Cited by:  Papers (118)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Recently published results have shown that, for many circuits, only a small percentage of path delay faults is robust testable. Among the robust untestable faults, a significant percentage of them is not non-robust testable either. In this paper, we take a closer look at the properties of these non-robust untestable faults with the goal of determining whether and how these faults should be tested View full abstract»

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  • Algorithms for cost optimised test strategy selection

    Publication Year: 1993, Page(s):383 - 391
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    This paper describes a system which aids designers in the selection of economically optimal design for testability strategies. The approach recognizes that design for testability decisions taken for parts of the circuit affect subsequent decisions for the design as a whole. Economics models are used to objectively evaluate strategies, and a set of algorithms is presented which provide efficient me... View full abstract»

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  • A built-in self-test for ADC and DAC in a single-chip speech CODEC

    Publication Year: 1993, Page(s):791 - 796
    Cited by:  Papers (41)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The performance characteristics of the ADC and the DAC designed in according with the CCITT recommendations are measured using BIST. Three characteristics have been evaluated and the measured results have shown good agreement with measured res... View full abstract»

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  • Certification trails and software design for testability

    Publication Year: 1993, Page(s):200 - 209
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    This paper investigates design techniques which may be applied to make program testing easier. We present methods for modifying a program to generate additional data which we refer to as a certification trail. This additional data is designed to allow the program output to be checked more quickly and effectively. Certification trails have heretofore been described primarily from a theoretical pers... View full abstract»

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  • Built-in current sensor for IDDQ test in CMOS

    Publication Year: 1993, Page(s):635 - 641
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper presents a current sensor circuit which can be built into a CMOS logic circuit to perform a self test for leakage current. The distinct features of the current sensor circuitry are described in detail. The circuit is verified by using the SPICE2 simulator View full abstract»

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  • Fault location algorithms for repairable embedded RAMs

    Publication Year: 1993, Page(s):825 - 834
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    This paper shows how to: (1) convert single-bit march tests into multi-bit March tests; and then (2) how to transform the new multi-bit March tests, using a "serial shifting notation" which represents "serial access" in embedded RAMs, into serial-access word-oriented March tests. The standard March test notation is extended to compactly include Galloping read actions, and other algorithms with two... View full abstract»

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  • A synthesis approach to design for testability

    Publication Year: 1993, Page(s):754 - 763
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    We present a new area-efficient procedure for embedding test function into the gate-level implementation of a sequential circuit. We use partition theory and a state variable dependency minimization criterion to map the test function states onto the states of the given circuit. The test generation complexity for our implementation is the same as that for a full scan design. To apply the method to ... View full abstract»

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  • Design-for-testability economics

    Publication Year: 1993
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    The need for design for testability (DFT) in mixed-signal boards and systems is becoming more significant as the miniaturization and superintegration trends continue. Accessibility to critical nodes of the circuits is required in order to meet the demands for higher quality, lower cost, shorter time to market, continuous improvement and standardization. However, we must be prudent in the way we ad... View full abstract»

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  • Structured CBIST in ASICS

    Publication Year: 1993, Page(s):332 - 338
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A novel method for automating the installation of CBIST and moving test development forward in the design cycle is shown, including a practical method for determining CBIST pathology. Three ASICS have been developed with this method. Design and prototype results are given View full abstract»

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  • Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs

    Publication Year: 1993, Page(s):865 - 874
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    This paper presents a study of the dynamic behavior of CMOS and BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering delay fault testing and results are compared with those achieved by means of functional testing. Electri... View full abstract»

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