[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

4-8 Jan. 1991

Filter Results

Displaying Results 1 - 25 of 62
  • Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design (Cat. No.91TH0340-0)

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (86 KB)
    Freely Available from IEEE
  • Compacting dead space in partitioning methods for random cells placements

    Publication Year: 1991, Page(s):273 - 274
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The partitioning methods for placement work by allocating cells to partition groups. The groups are then further partitioned until the number of cells allocated to each group is small enough to be handled efficiently by other placement methods. The authors introduce extended channel constraint (ECC) graphs, a concept extended from Lauther's channel constraint graphs. The ECC graphs lead to a metho... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A class of hierarchical networks for VLSI/WSI based multicomputers

    Publication Year: 1991, Page(s):267 - 272
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A class of hierarchical networks is proposed for multicomputer implementation using VLSI and wafer scale integration (VLSI/WSI). These networks, called DBCube, connect clusters of cube topology based nodes with a De Bruijn graph. The nodes are identical and can be easily extended to a larger size. The cube topology for local communication allows easy embedding of parallel algorithms and the De Bru... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new processor interconnection structure for fault tolerant processor arrays

    Publication Year: 1991, Page(s):261 - 266
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the tradition... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automated data path synthesis to avoid global interconnects

    Publication Year: 1991, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in la... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Yield and layout issues in fault tolerant VLSI architectures

    Publication Year: 1991, Page(s):255 - 260
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Yield and layout are two important but often ignored issues in the design of fault tolerant VLSI systems. The authors present a framework for the systematic analysis of yield and area-efficient layout of fault-tolerant architectures. A multiple level redundancy tree is considered as a target architecture to demonstrate their analysis technique View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generic component library characterization for high level synthesis

    Publication Year: 1991, Page(s):5 - 10
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Describes a novel generator-generator environment for characterizing generic component libraries used in high level hardware synthesis. The environment is composed of LEGEND, a language used to specify generic libraries, and GENUS, the generated generic component library. GENUS provides generic component instances for the task of behavior-to-structure mapping in high level synthesis. The LEGEND/GE... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An algorithm for minimising the number of test cycles

    Publication Year: 1991, Page(s):154 - 156
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A VLSI routing framework for use on a multiprocessor workstation

    Publication Year: 1991, Page(s):82 - 87
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    With the coming of age of CAD workstations based on parallel hardware and the increasing need to accelerate CAD tools, there is a demand to exploit parallelism on general-purpose parallel hardware to achieve speedup. Hence, a novel VLSI routing framework was investigated for a parallel CAD workstation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel integrated scheduling and allocation algorithm for data path synthesis

    Publication Year: 1991, Page(s):212 - 218
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Proposes a novel integrated scheduling and allocation algorithm suitable for automatic data path synthesis. The algorithm is based on computation of an accurate lower bound on the cost of functional units. The algorithm produces optimal schedules in most cases View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Monte Carlo simulation environment for wear out in VLSI systems

    Publication Year: 1991, Page(s):249 - 254
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switchin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new test scheduling algorithm for VLSI systems

    Publication Year: 1991, Page(s):148 - 153
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A systolic chip for LZ based data compression

    Publication Year: 1991, Page(s):310 - 311
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throug... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulated annealing-based channel routing on hypercube computers

    Publication Year: 1991, Page(s):75 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottleneck in designing complex chips, due to the inherent compute-intensive nature of this task. Parallel processing of the routing problem holds promise for mitigating this situation. The authors present a parallel channel routing algorithm that is targetted to run on loosely coupled computers like hypercu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of high-speed VLSI circuits for mainframe computers

    Publication Year: 1991, Page(s):206 - 211
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    The next generation of mainframe computers will use fast BiCMOS ASICS having upto 100000 gate functions. Static CMOS RAMs with 3 ns access time will be embedded in bipolar ECL logic circuits with 50 ps gate delay. Standard cells will be intensively applied in order to obtain very fast macros with reduced power and space. Delay rules have to be designed in order to predict net delay and delay toler... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defect and design error location procedure-theoretical basis

    Publication Year: 1991, Page(s):243 - 248
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient testing techniques for bit and digit-serial arrays

    Publication Year: 1991, Page(s):142 - 147
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Bit and digit-serial architectures are used extensively in digital signal processing applications. Testing these structures is a very difficult problem due to low controllability/observability and complex interconnections between the circuit components. Efficient test generation techniques have been developed and applied to three classes of bit and digit-serial circuits. The testing techniques are... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • YAQT: Yet another quad tree

    Publication Year: 1991, Page(s):302 - 309
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A new data structure for storing two dimensional objects has been presented. A multiple storage quad tree is a quad tree which stores pointers to objects intersecting more than one quad in all of the quad that they intersect. The YAQT (Yet Another Quad Tree) is a modified form of multiple storage quad tree with no list required for storing crossing objects. A substantial improvement in the region ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and performance evaluation of high-resolution oversampling A/D converters

    Publication Year: 1991, Page(s):297 - 298
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    An approach to the behavioural simulation of ΣΔ A/D converters is presented. Integrator, comparator and digital filtering blocks are implemented with the advantage of being easily interfaced with component designers. Post-processing algorithms for overall performance evaluation are also discussed, specially by focusing on the fact they can largely affect the meaning of the results. Sim... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Method for testable design and for built-in test

    Publication Year: 1991, Page(s):286 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel test pattern generation using Boolean satisfiability

    Publication Year: 1991, Page(s):69 - 74
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on Boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. This paper suggests parallel versions of Larrabe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multilevel simulation tool for designing fault-tolerant VLSI array processors

    Publication Year: 1991, Page(s):293 - 294
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    The authors present the design details of an integrated CAD tool for efficient realization of parallel processors for high throughput in real-time digital signal processing (DSP) applications. The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level. Core of this tool is a functional-structural s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of a control unit from instruction set specification in VHDL environment

    Publication Year: 1991, Page(s):200 - 205
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Automated design of control structures for digital systems has been one of the active areas of research in high level synthesis. This paper proposes a methodology for specifying an instruction set in VHDL and also presents a system for synthesizing controller for the target processor. The goal of this system is to serve as a tool to help in early evaluation of instruction sets for implementation i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of ASIC datapath compilers for gate array designs

    Publication Year: 1991, Page(s):281 - 282
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    The authors present a complete development flow of ASIC datapath compilers for gate array designs. The module design and usage flow for the parameterized datapath elements is described. The efficiency achieved through the use of a highly integrated design environment is highlighted View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ATPG with efficient testability measures and partial fault simulation

    Publication Year: 1991, Page(s):35 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Proposes an improved version of the test generation algorithm PODEM path oriented decision-making incorporating a different technique for backtracing and forward implication. The authors also propose a partial fault simulator which is integrated into the improved PODEM algorithm. The performance of this test generation package (when partial fault simulator is employed) is compared to that of a con... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.