[Proceedings] EURO ASIC `90

May 29 1990-June 1 1990

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Displaying Results 1 - 25 of 90
  • EURO ASIC '90 (Cat. No.90TH0316-0)

    Publication Year: 1990
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    Freely Available from IEEE
  • Application of digital CMOS ASICs in a medical diagnostic imaging design

    Publication Year: 1990, Page(s):310 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A new line of medical diagnostic imaging instruments was designed using application-specific integration as a key technology. An outstanding price-performance ratio can be achieved using a system integration approach. Development- and production-costs are discussed, given the case of a low volume/high complexity product View full abstract»

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  • A parallel processor ASIC for real time pattern recognition

    Publication Year: 1990, Page(s):306 - 309
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A real time pattern processing ASIC is described. By exploiting a 1 u, 3.3 V DLM CMOS technology, a 10 MHz 250 k transistor chip was designed for machine vision applications requiring recognition of objects in real time. The architecture, design, simulation methodology, and test strategy of the chip is discussed View full abstract»

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  • A test strategy for mixed analog/digital ASICS

    Publication Year: 1990, Page(s):300 - 304
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    Typical examples of analog functions and their testing are described. It is shown, that these tests can be performed on digital testers. A test strategy for mixed ASICs is proposed, as an extension of techniques applicable to digital ASICs View full abstract»

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  • The microprocessor support peripheral family and the direct access test methodology

    Publication Year: 1990, Page(s):365 - 369
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    Designs using LSI peripherals could have testability problems when peripheral I/O's are embedded within the design. A designer must contend with both lack of circuit knowledge and time when developing production test programs for new LSI ASIC offerings. This paper will introduce Intel's microprocessor support peripheral family and the direct access test scheme (DAT). The DAT was developed to isola... View full abstract»

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  • Analog-digital integrated test concerns

    Publication Year: 1990, Page(s):296 - 299
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    Considers the practical test issues concerned with design verification of prototype mixed signal components. Mixed signal testing is treated as an extension to familiar digital test techniques View full abstract»

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  • VLSI area estimation tolerances-shape function generation vs. floorplanning

    Publication Year: 1990, Page(s):202 - 207
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    Area estimation is an important task during the planning of VLSI systems. Several methods have been proposed. But how can one determine the reliability of an estimate? Can an estimate be 100% correct? The answer is no because the design process is not fully predictable. The predictability is an upper limit for the reliability of estimates. Reliability and predictability are defined and examples gi... View full abstract»

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  • Crosspoint element: Elemento de Cruce (EC)

    Publication Year: 1990, Page(s):163 - 166
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    The VLSI integrated circuit “Elemento de Cruce” (EC) has been conceived as a multifunction device. The EC has been designed to work as the crosspoint element in a broadband (ATM) asynchronous transfer mode (ATM) switch block, as well as an interfacing device between a microprocessor, a codec or, in general, any data source and the ATM switch network. The EC works at a frequency of 43.7... View full abstract»

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  • Latch-up characterization of semicustom using ATE

    Publication Year: 1990, Page(s):439 - 443
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    An ATE approach for latch-up static test is proposed that allows a quick and complete characterization of devices even with a very high pin count. The software tool is described and some results presented View full abstract»

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  • Autodiagnosis speeds turn around time

    Publication Year: 1990, Page(s):362 - 364
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    As gate arrays become more complex, the test vector generations effort increases in an alarming fashion. This problem has existed for some time, and there have been many attempts at devising a solution. This paper describes Hitachi's autodiagnosis concept, which has proved to be enormously successful. Gate array development has now reached a stage of some maturity, and very high densities are bein... View full abstract»

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  • Automatic generation of analog test programs

    Publication Year: 1990, Page(s):290 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A fast, competitive CAD-procedure requires a high degree of automatization that also includes the generation of the test program. Starting with an analog test plan written by the user and a circuit description, a test program is generated automatically for analog circuits and for the analog part of hybrid circuits. The test program is synthesized from different, proven software modules. The additi... View full abstract»

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  • An ASIC controller for the TMS 320, 2-generation digital signal processor

    Publication Year: 1990, Page(s):197 - 200
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA View full abstract»

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  • A semi-custom pad library

    Publication Year: 1990, Page(s):456 - 460
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Describes the design of a pad library for a semi-custom array family. It discusses the requirements defined by the application environment of semi-custom arrays. These requirements are subsequently translated into components and their respective characteristics. Three types of pads are distinguished: (1) power pads; (2) input, output, bi-directional and tri-state pads; and (3) special pads. The de... View full abstract»

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  • KIM 20: a symbolic RISC microprocessor for embedded advanced control

    Publication Year: 1990, Page(s):160 - 162
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    The author describes a new microprocessor architecture designed applying artificial intelligence techniques in complex process control applications. The KIM 20 embedded RISC microprocessor is a first implementation based on a classic CMOS 1.5 micron technology. Firstly the application field is introduced and secondly a technical overview of the architecture is given. Then, he discusses the ASIC to... View full abstract»

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  • Thin film transistors modeling and parameters extraction tool

    Publication Year: 1990, Page(s):436 - 438
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    Presents a parameters extraction tool for transistors modeling activity, which gives way to characterize not only MOS processes but also to check and validate four terminal transistor models such as polysilicon thin film transistors View full abstract»

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  • Anatem Version-2-A CMOS timing analyzer for static CMOS networks

    Publication Year: 1990, Page(s):354 - 359
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    A new timing analyzer has been developed. It is able to work at the transistor level, to be back-annotated from the layout, to deal with sequential and combinational logic. The physical way to model the internal timing behavior of a gate, (RC)int, and the use of the least square method to fit experimental and theoretical results, leads to a global accuracy between 10-15% when compared to Eldo [HEN... View full abstract»

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  • A floating-point systolic array processing element using serial communication

    Publication Year: 1990, Page(s):240 - 243
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The authors describe the design of a processing element (PE) for systolic array applications. The PE which is configured as a multiplier-accumulator or an inner product step processor, supports most common systolic algorithms in signal processing and matrix arithmetic. Communication with neighbouring PEs is achieved through 18 on-chip serial links, each operating at 50 Mb per second. The 30 K tran... View full abstract»

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  • A hierarchical behavioural description based CAD system

    Publication Year: 1990, Page(s):282 - 287
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Describes the hierarchical behavioral description language called SFL and its processing system. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clock-synchronized circuits. The main features of SFL are as follows: (1) It is not mixed with connection description, but employs only behavioral description (like procedural description in progr... View full abstract»

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  • A mixed analog/digital ASIC for real time spectrum analysis

    Publication Year: 1990, Page(s):192 - 195
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    A circuit dedicated to real time spectrum analysis has been implemented in a 3 microns CMOS technology. Power spectral density is measured with an error of less than 1% in a frequency range from 100 Hz to 50 kHz. Specific dynamic offset reduction techniques have been developed for the full custom analog part. Real time programming is possible through the standard cell digital part View full abstract»

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  • Built-in self-test for generated blocks in an ASIC environment

    Publication Year: 1990, Page(s):320 - 325
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Techniques for Built-in Self-Test of RAMs embedded within ASIC's are presented. The test algorithm (sequence) has been laid out with emphasis on high fault coverage and low silicon overhead. It supports existing RAM generator tool and allows for generating a wide spectrum of possible configurations. The BIST circuit itself is a soft-macro built from standard library elements. The schematic will be... View full abstract»

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  • Global routing driven floorplanning

    Publication Year: 1990, Page(s):214 - 219
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A novel global routing driven floorplanning approach is presented. Rectangular cells such as in macrocell design are considered. The major contributions of the paper are: (1) a new model for the prediction of shape functions which enables one to consider a more general class of floorplan representations. (2) An improved two-dimensional partitioning procedure. (3) A dynamic updating scheme that con... View full abstract»

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  • Standard cell development flow

    Publication Year: 1990, Page(s):450 - 455
    Cited by:  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Describes the new standard-cell development flow, being used at Philips Components Nijmegen. The new flow will integrate all aspects of developing a standard-cell library into one program, resulting in a dramatic decrease in development effort and providing the user with a quick release of an errorfree library. Quality is maintained by virtue of a built-in quality control tool. A stick-editor will... View full abstract»

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  • Verifying ASICs by symbolic simulation

    Publication Year: 1990, Page(s):468 - 473
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A new tool which is capable of dealing with digital circuit designs on a functional, or behavioural, level is presented. The tool has been used extensively in a design center for ASICS, and several real-life applications of it are described. The basis of the new tool is formed by efficient algorithms for manipulating Boolean functions and finite-state machines. Among the applications of the tool a... View full abstract»

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  • A new algorithm for diagnosis-oriented automatic test pattern generation

    Publication Year: 1990, Page(s):332 - 336
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Production testing does not only aim at detecting faulty devices, but its goals are often to repair the element or to investigate the cause of failure, so as to tune the manufacturing process. Diagnostic testing is thus becoming the object of attention both in industry and academia, thanks also to the increased power of tools like fault simulators, testability analysers, and ATPGs. Diagnostic test... View full abstract»

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  • Silicon compilation of algorithm structures

    Publication Year: 1990, Page(s):480 - 484
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    This paper describes the design of the Kiwi processor, which hardwires a new efficient unification algorithm for PROLOG resolution, using high-performance silicon compilers of VLSI Technology, Inc. Moreover, a new method for high-level simulation has been performed and appears to be best suited for complex design reliability check View full abstract»

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