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International Test Conference 1988 Proceeding@m_New Frontiers in Testing

12-14 Sept. 1988

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Displaying Results 1 - 25 of 134
  • Concurrent control of multiple BIT structures

    Publication Year: 1988, Page(s):431 - 442
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    A generic control graph for activating common built-in test structures is derived and its microprogrammed and hardwired implementations described. Three designs for activating multiple BIT structures concurrently are also presented along with simulation results of area/test time tradeoffs. Two designs for this generic controller are presented. The first design augments the classical microprogramme... View full abstract»

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  • International Test Conference 1988 Proceedings - New Frontiers in Testing (Cat. No.88CH2610-4)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (24 KB)
    Freely Available from IEEE
  • Elimination of incoming test based upon in-process failure and repair costs

    Publication Year: 1988, Page(s):308 - 313
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB)

    An economic model was developed that challenges traditional statistical quality-control methods in the factory. Incoming inspection levels can be determined as a function of both the PPM (parts per million) quality level and the lot-to-lot stability. When incoming quality levels fall to below 100 PPM, the model can be used to reevaluate conventional test strategies in high volume manufacturing ope... View full abstract»

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  • D3FS: a demand driven deductive fault simulator

    Publication Year: 1988, Page(s):582 - 592
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    A high-speed fault simulator is presented that combines demand-driven simulation techniques with a bit-encoded deductive fault simulation scheme. The simulator uses an efficient approach to the management of signal value and fault list structures intended to minimize disk thrashing during execution. Input cone analysis is used during preprocessing to identify gates with independent inputs so that ... View full abstract»

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  • Error detection with latency in sequential circuits

    Publication Year: 1988, Page(s):926 - 933
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    An approach is proposed to encoding states of sequential circuits that takes advantage of the concept of error detection with latency, and which is applicable to a much broader class of sequential machines. An encoding methodology is introduced that uses tree codes for online detection of sequencing errors with latency in sequential circuits. This approach has the potential to yield designs with l... View full abstract»

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  • Key technologies for 500-MHz VLSI system ULTIMATE

    Publication Year: 1988, Page(s):108 - 113
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5 K-gate and 400-gate ultrahigh-speed ... View full abstract»

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  • Switch-level concurrent fault simulation based on a general purpose list traversal mechanism

    Publication Year: 1988, Page(s):574 - 581
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A general-purpose traversal mechanism is described which is used to perform concurrent simulation for complex devices. This traversal mechanism performs all list handling necessary for an accurate and efficient concurrent simulation at a complexity level much higher than that of the gate level. The work on this general-purpose traversal mechanism project has been done within the DECSIM logic simul... View full abstract»

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  • Multiple distributions for biased random test patterns

    Publication Year: 1988, Page(s):236 - 244
    Cited by:  Papers (74)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    An efficient method has been presented to compute multiple distributions for random patterns, which can be applied successively. Using multiple distributions, all combinational circuits can be made random-testable, and complete fault coverage is provided by a few thousands of random patterns. The differently weighted random test sets can be applied to scan path circuits using an external chip, com... View full abstract»

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  • Delay test generation. II. Algebra and algorithms

    Publication Year: 1988, Page(s):867 - 876
    Cited by:  Papers (34)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using actual gate delays). A test generator uses this alg... View full abstract»

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  • Continuous signature monitoring: efficient concurrent-detection of processor control errors

    Publication Year: 1988, Page(s):914 - 925
    Cited by:  Papers (23)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    Concurrent detection of processor control errors using signatured programs is discussed. The approach, called continuous signature monitoring (CSM), makes significant advances beyond the existing signature-monitoring techniques. For typical programs, CSM decreased average error-detection latency by as much as eight times, down to 1.2 to 1.6 program memory cycles. Memory overhead for storing signat... View full abstract»

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  • A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

    Publication Year: 1988, Page(s):102 - 107
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs u... View full abstract»

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  • Stuck-open and transition fault testing in CMOS complex gates

    Publication Year: 1988, Page(s):688 - 694
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used t... View full abstract»

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  • Fault bundling: reducing machine evaluation activity in hierarchical concurrent fault simulation

    Publication Year: 1988, Page(s):569 - 573
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A method of bundling error data is proposed which should significantly reduce the amount of explicit functional evaluation required for hierarchical concurrent simulation. The bundling operation is carried out at run time, and so is different from but complementary to approaches such as WRAP, which compress unnecessary or uninteresting portions of circuit hierarchy. The technique is exact; it does... View full abstract»

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  • The KARL/KARATE system-automatic test pattern generation based on RT level descriptions

    Publication Year: 1988, Page(s):230 - 235
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A system is described for automatic test-pattern generation (ATPG) using symbolic representations and heuristics to attack the test problem at RT level, where redesigns to increase the testability are relatively cheap. In contrast to other ATPG tools based on RT-level hardware descriptions, KARATE includes tests for primitive operators and allows the modification and redefinition of fault models. ... View full abstract»

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  • Delay test generation. I. Concepts and coverage metrics

    Publication Year: 1988, Page(s):857 - 866
    Cited by:  Papers (64)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    An approach to test for delay faults is presented. A variable size delay fault model is used to represent these failures. The nominal gate delays with the manufacturing tolerances are an integral part of the model and are used in the propagation of simplified waveforms through the logic network. The faulty waveforms are functions of the variable-size delay fault. For each fault and test pattern, a... View full abstract»

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  • Electron beam tester integrated into a VLSI tester

    Publication Year: 1988, Page(s):908 - 913
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    An integrated EB (electron-beam) testing system is constructed for precise failure analysis and reduction of total testing time, coupling a VLSI tester and an EB tester. Unique features of the system are briefly described, together with its system configuration and functions. The close connection of LSI testing and EB testing environments is further continued. It is planned to improve the integrat... View full abstract»

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  • Characteristic impedance and coupling coefficients for multilayer PC boards

    Publication Year: 1988, Page(s):28 - 38
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Novel equations giving electrical parameters from printed circuit (PC) board trace geometries are presented. Computed characteristic impedance, coupling capacitance, and inductive coupling coefficient are experimentally investigated using a wide variety of stripline and microstrip geometries. These parameters apply to SPICE models of circuits on PC boards containing fast (ns) devices View full abstract»

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  • CAD tools for supporting system design for testability

    Publication Year: 1988
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed t... View full abstract»

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  • Fault simulation and test pattern generation at the multiple-valued switch level

    Publication Year: 1988, Page(s):94 - 101
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A fault simulation and test-pattern-generation environment is specified. It includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The authors' main idea is to define what is possible when no extraction to gate level and no creation of transistor groups are performed. Two fault groups are distinguished: the faults whic... View full abstract»

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  • In-circuit test fixture

    Publication Year: 1988, Page(s):391 - 400
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Two failure modes are identified for the conventional in-circuit fixture. The fixture is compared with a conventional fixture and is found to be superior. The fixture provides a coaxial-like raceway to propagate signals. Crosstalk and mismatch are greatly reduced View full abstract»

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  • Design for test and the cost of quality

    Publication Year: 1988, Page(s):302 - 307
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A generalized methodology is presented which can be used to select a cost effective design-for-test technique for use in the design process. The intent is to factor in both increased research and development costs as well as increased production costs. The authors also correlate the expected levels of test coverage. Thus, for a particular design, it is possible to predict the increase in cost of r... View full abstract»

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  • Do the designs work? [VLSI design education]

    Publication Year: 1988, Page(s):207 - 208
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    The author presents a philosophy of VLSI design education based on four premises: managing a VLSI design requires a hierarchical approach; a library of standard cells simplifies and increases design reliability; VLSI design requires interaction between the designer and a supportive CAE (computer-aided engineering) environment; and to allow reliable design by inexperienced designers, the CAE enviro... View full abstract»

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  • What is the path to fast fault simulation?

    Publication Year: 1988, Page(s):183 - 192
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Motivated by the advances in fast fault-simulation techniques for large combinational circuits, a panel discussion was organized for the 1988 International Test Conference. A collective account of the position statements is offered by the panelists. The panelists present discussions on the following topics: introduction to fault simulation; parallel pattern fault simulation; intelligent heuristics... View full abstract»

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  • New automated prober support for high pincount test heads

    Publication Year: 1988, Page(s):615 - 620
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Automatic best-fit tip-to-pad alignment and skewed chip probing based on high-speed image processing is described. A complete solution is presented to automate and optimize the probe set up. It can be implemented as operator assist or as total automation, depending on the status of the local system. It is concluded that high-speed image processing techniques should also be able to keep pace with t... View full abstract»

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  • An algorithmic branch and bound method for PLA test pattern generation

    Publication Year: 1988, Page(s):784 - 795
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB)

    A method for PLA (programmable logic-array) test-pattern generation based on a branch-and-bound algorithm that function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models, in... View full abstract»

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