IEEE Proceedings of the Custom Integrated Circuits Conference

13-16 May 1990

Filter Results

Displaying Results 1 - 25 of 168
  • A 30000 gate ECL gate array using advanced single poly technology and four level metal interconnect

    Publication Year: 1990, Page(s):4.4/1 - 4.4/4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB)

    The architecture and fabrication of a 30000 emitter coupled logic (ECL) gate array featuring a 90-ps unloaded gate delay are described. Current mode logic (CML) and ECL macros can be combined on custom-defined chips to minimize power without compromising the performance. The product has a channelless ocean-of-cells architecture permitting 100% cell utilization with ECL 100 K and 10 K I/O interface... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A hybridised, multi-channel, charged-particle detecting and counting array

    Publication Year: 1990, Page(s):15.7/1 - 15.7/4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB)

    A hybrid circuit is reported which is a novel position-sensitive charged-particle detector. Multiple-anode integrated detectors (MAIDs) have been developed which consist of an array of electron sensing anodes and a corresponding array of amplifiers and counters all integrated on a single chip. The anodes are fabricated on the surface of the chip over a thick dielectric film. The active anode array... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparative performance limits of MOSFET, MESFET and MODFET digital circuits

    Publication Year: 1990, Page(s):18.8/1 - 18.8/4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Using the static transfer curves derived from analytical drain current and threshold voltage models for short-channel MOSFETs, MESFETs and MODFETs, the FET scaling limits in CMOS and E/D MOSFET (NMOS), MESFET, and MODFET DCFL digital circuits are determined as 0.025 mu m, 0.05 mu m, 0.075 mu m, and 0.075 mu m (respectively) from noise margin considerations. The corresponding delay times of ring os... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Proceedings of the IEEE 1990 Custom Integrated Circuits Conference (Cat. No.90CH2860-5)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (1232 KB)
    Freely Available from IEEE
  • Integrated sensor and rangefinding analog signal processor

    Publication Year: 1990, Page(s):7.1/1 - 7.1/6
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A light-stripe rangefinding system consisting of a 6×10 array of pixels is described. Each pixel contains a photodiode to detect the light stripe and a primarily analog signal processor to determine and store the time at which the light stripe crosses that photodiode. Incorporating signal processing into each pixel makes it possible to modify the light-stripe rangefinding algorithm to achiev... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-cost CMOS algorithmic digital-analogue convertor for high-frequency applications

    Publication Year: 1990, Page(s):6.7/1 - 6.7/4
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A novel, low-cost digital-analog convertor (DAC) circuit suitable for high-frequency applications has been designed and integrated using a 2.5-μm CMOS technology. The convertor uses a purely passive parasitic-compensated switched-capacitor circuit to implement a conversion algorithm consisting of a mere charge division between equal-valued capacitors. The output voltage signal directly related ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high speed EEPROM configurable digital to analog convertor array

    Publication Year: 1990, Page(s):6.6/1 - 6.6/5
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    A project to develop a new generation of letter-sorting machines for use in government postal centers and commercial applications was undertaken. A special purpose EEPROM configurable digital-to-analog convertor (DAC) chip used in an optical recognition system is described. The chip was optimized for high-speed DAC response (>25 ns) and high current switching of the DAC array with a DAC lineari... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Labyrinth: a homogeneous computational medium

    Publication Year: 1990, Page(s):31.1/1 - 31.1/4
    Cited by:  Papers (5)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    As a RAM-based reconfigurable logic array, Labyrinth provides the flexibility and malleability of software with the performance of a dedicated circuit. With a single bit register and a half adder per cell, the architecture is optimized for register intensive, massively parallel algorithms. The fine-grained, highly-symmetric architecture scales very naturally and facilitates compact circuit layouts... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated ASIC diagnosis system

    Publication Year: 1990, Page(s):19.1/1 - 19.1/4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The scanning electron microscope design analyzer (LSEM) is an integrated system consisting of a VLSI tester, an electron beam prober, and a modular design automation software. This system provides a user-friendly workstation environment for the complete analysis and debug of complex, submicron ASICs. LSEM has been successfully used to analyze the functional operation and internal timing of many co... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic synthesis of analog and sampled-data circuits in CMOS technology

    Publication Year: 1990, Page(s):14.7/1 - 14.7/4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A tool for the design and implementation of analog CMOS and switched-capacitor (SC) networks is described. It requires a set of specifications and a circuit description of each SC block. It generates the requirements of an operational amplifier for each SC block, and designs and evaluates the performance of operational amplifier through iteration with SPICE. The result is a stand-alone layout of a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 7-channel level generator chip for a VLSI digital tester

    Publication Year: 1990, Page(s):6.5/1 - 6.5/4
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    The automatic test equipment (ATE) level generator chip integrates all the per-pin analog levels required in a VLSI digital tester. This system chip was specified and defined at an architectural level by ATE engineers and implemented using a building block approach by the semicustom supplier working from standard function cells. The chip is integrated on an n-well junction-isolated merged bipolar-... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Behavioral analog circuit models for multiple simulation environments

    Publication Year: 1990, Page(s):5.5/1 - 5.5/4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A method for modeling analog circuits at the behavioral level using nonlinear differential equations is described. The resulting models execute efficiently in various simulation environments, including a circuit analysis program and an event-driven logic simulator. Behavioral models are expressed as differential equations with respect to time. A variety of linear and nonlinear operators are provid... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic verification of library-based IC designs

    Publication Year: 1990, Page(s):30.6/1 - 30.6/5
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A novel method for fully automatic verification of layout generated by means of a library is presented. It is based on the bottom-up reconstruction of the architecture level, starting from layout. The benefits have been confirmed during the verification of VLSI circuits generated with the PIRAMID silicon compiler. Previously unnoticed design and synthesis errors have been detected in a very effici... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • FIRGEN: a CAD system for automatic layout generation of high-performance FIR filter

    Publication Year: 1990, Page(s):14.6/1 - 14.6/4
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A novel functional compiler, FIRGEN, for automatic generation of finite-impulse response (FIR) filters using custom and gate-array technologies is described. It consists of CAD tools to automate the entire design from filter specifications to final chip layout. The architecture and floorplan description generation by FIRGEN can be used to drive custom macrocell or gate-array place and route tools ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 8-b 50-MHz 225-mW submicron CMOS ADC using saturation eliminated comparators

    Publication Year: 1990, Page(s):6.4/1 - 6.4/4
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The fastest, low-power 8-b CMOS subranging A/D converter with a 50-MHz conversion rate and 225-mW power consumption is realized using 0.8-μm CMOS technology. The comparator used in the converter has a saturation elimination circuit, which eliminates the comparison delay caused by saturation. This circuit is useful for improving conversion speed or reducing converter power consumption. It is als... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Direct solution of performance constraints during placement

    Publication Year: 1990, Page(s):27.2/1 - 27.2/4
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    A practical set of features for meeting the constraints of high performance designs during placement has been developed. The tool observes signal path constraints in units of time, automatically trading off delay between nets on the critical paths. The tool can observe net constraints in units of delay or capacitance. These features are based on a fast and accurate algorithm for net wiring estimat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of a neuron dedicated to Kohonen maps with learning capabilities

    Publication Year: 1990, Page(s):26.1/1 - 26.1/4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A compact implementation of Kohonen-oriented neurons with learning capability, using both analog and digital techniques, with standard low-cost CMOS technologies, is described. Each synaptic weight is stored as a discrete voltage on a capacitor. Leakage currents are compensated by a special circuitry, which is also used for learning. Input signals are frequency-coded pulse streams, and the synapti... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimation of power dissipation in CMOS combinational circuits

    Publication Year: 1990, Page(s):19.7/1 - 19.7/6
    Cited by:  Papers (23)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    It is shown that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, algorithms are given for transforming the problem to a weighted max-satisfiability problem, and then exact and approximate algorithms f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of an analog hardware description language

    Publication Year: 1990, Page(s):5.4/1 - 5.4/6
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Network description languages are reviewed, and some of the required features of a standard analog hardware description language (AHDL) are defined. Modifications to IEEE 1076 standard VHDL are proposed in order to create a prototype AHDL. An example circuit description is given. The motivations for the development of a standardized AHDL are threefold. First, such a language would support a hierar... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A dynamic CMOS multiplier for analog neural network cells

    Publication Year: 1990, Page(s):26.4/1 - 26.4/4
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A strobed multiplier circuit for use in integrated neural network architectures is presented. The circuit, which can be fabricated in a standard CMOS analog process, performs the two-quadrant weighting of interconnect signals via exponential charge packets onto capacitive summing buses. SPICE simulations and MOSIS fabrication results are presented. The proposed design is simple in structure, uses ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-speed CMOS amplifier with dynamic frequency compensation

    Publication Year: 1990, Page(s):8.4/1 - 8.4/4
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    High-performance CMOS operational amplifiers with advanced frequency compensation, dynamic biasing, and enhanced slew rate are presented. Prototyping amplifiers with three design techniques have been fabricated by the MOSIS service using a 2-μm scalable CMOS technology. Experimental results show a significant speed-up on amplifier transient responses. The dynamic biasing technique is used to en... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transformation-based layout optimization

    Publication Year: 1990, Page(s):30.5/1 - 30.5/4
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    An approach to layout optimization that involves invoking a set of transformations on an initial symbolic layout is presented. The tools work well together, providing a high degree of user-controllability. The tools run on selected areas or the whole chip, honor the user's modifications, perform with partial layouts and ERC/LVS errors, and have separate and clearly defined optimizations. The tools... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic synthesis of asynchronous circuits

    Publication Year: 1990, Page(s):29.6/1 - 29.6/4
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    A synthesis method and a CAD program to provide racefree asynchronous CMOS circuits that are independent of the internal and output delays are presented. The method minimizes the number of transitions between stable states and the number of gates, providing new cells for fast and low-power integrated circuits. Without any additional cost, the circuit will present neither critical races nor hazards... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A knowledge based simulation environment

    Publication Year: 1990, Page(s):10.6/1 - 10.6/4
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A knowledge-based shell for simulators has been developed as one part of a design environment for analog circuits. This shell offers circuit-specific simulation support exploiting expert knowledge for dealing with problems like test function generation and simulation clustering. Applications areas are all domains that require automated circuit characterization, such as synthesis or cell library ma... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Turn-on transient imposed extrinsic base consideration in BiNMOS transistors

    Publication Year: 1990, Page(s):18.7/1 - 18.7/4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    A detailed two-dimensional numerical simulation study on the bipolar devices in the BiCMOS circuit environment during turn-on transient is presented. The unique charge build-up and removal phenomenon in the bipolar device determines the switching speed of the BiNMOS devices. The tradeoffs in designing the extrinsic base in terms of the switching behavior are described. It is shown that the structu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.