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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

10-12 Nov. 2004

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  • HLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and Test

    Publication Year: 2004, Page(s): 0_1
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    Publication Year: 2004, Page(s): 0_2
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  • Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

    Publication Year: 2004
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  • Copyright

    Publication Year: 2004, Page(s): ii
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  • Chairs' welcome message

    Publication Year: 2004, Page(s): iii
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  • Committees

    Publication Year: 2004, Page(s): iv
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  • Table of contents

    Publication Year: 2004, Page(s):v - viii
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  • TTTC: test technology technical council

    Publication Year: 2004, Page(s):ix - xi
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    Publication Year: 2004, Page(s): xii
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  • Session 1: formal techniques

    Publication Year: 2004, Page(s): 1
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    Publication Year: 2004, Page(s): 2
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  • Enhancing sequential depth computation with a branch-and-bound algorithm

    Publication Year: 2004, Page(s):3 - 8
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (519 KB) | HTML iconHTML

    We present an effective algorithm to enhance sequential depth computation. The sequential depth plays the most crucial role to the completeness of bounded model checking. Previous work computes the sequential depth by exhaustively searching the state space, which is unable to keep pace with the exponential growth of design complexity. To improve the computation, we develop an efficient approach th... View full abstract»

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  • Reference model based RTL verification: an integrated approach

    Publication Year: 2004, Page(s):9 - 13
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (485 KB) | HTML iconHTML

    We present an approach that makes reference model based formal verification both complete and practical in an industrial setting. This paper describes a novel approach to conduct this exercise, by seamlessly integrating formal equivalence verification (FEV) techniques within a verification flow suited to formal property verification (FPV). This enables us to take full advantage of the rich express... View full abstract»

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    Publication Year: 2004, Page(s): 14
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  • Dynamic guiding of bounded property checking

    Publication Year: 2004, Page(s):15 - 18
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (441 KB) | HTML iconHTML

    Current statistics attribute up to 75% of the overall design costs of digital hardware and embedded system development to the verification task. In recent years, the trend to augment functional with formal verification tries to alleviate this problem. Efficient property checking algorithms allow automatic verification of middle-sized designs nowadays. However, the steadily increasing design sizes ... View full abstract»

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  • Towards an efficient assertion based verification of SystemC designs

    Publication Year: 2004, Page(s):19 - 22
    Cited by:  Papers (11)  |  Patents (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (452 KB) | HTML iconHTML

    In this paper, we present an approach to verify efficiently assertions added on top of the SystemC library and based on the property specification language (PSL). In order to improve the assertion coverage, we also propose an approach based on both static code analysis and genetic algorithms. Static code analysis will help generate a dependency relation between inputs and assertion parameters as w... View full abstract»

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  • Session 2: processor-oriented validation

    Publication Year: 2004, Page(s): 23
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    Publication Year: 2004, Page(s): 24
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  • Instruction level test methodology for CPU core software-based self-testing

    Publication Year: 2004, Page(s):25 - 29
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (430 KB) | HTML iconHTML

    TIS (S. Shamshiri et al., 2004) is an instruction level methodology for CPU core self-testing that enhances the instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions so that online testing can be done with no performance penalty. TIS tests different parts of the CPU a... View full abstract»

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    Publication Year: 2004, Page(s): 30
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  • Simplifying design and verification for structural hazards and datapaths in pipelined circuits

    Publication Year: 2004, Page(s):31 - 36
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (604 KB) | HTML iconHTML

    This paper describes a technique that automates the specification and verification of structural-hazard and datapath correctness properties for pipelined circuits. The technique is based upon a template for pipeline stages, a control-circuit cell library, a decomposition of structural hazard and datapath correctness into a collection of simple properties, and a prototype design tool that generates... View full abstract»

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  • ATPG based functional test for data paths: application to a floating point unit

    Publication Year: 2004, Page(s):37 - 40
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (436 KB) | HTML iconHTML

    Application of an ATPG based functional test methodology that is tailored towards data paths to a floating point unit is described. The methodology employs the instruction set of the processor to control the inputs and to observe the outputs of the data path and utilizes an ATPG tool to generate test patterns. The test patterns are then converted to instruction sequences and applied as a functiona... View full abstract»

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  • Formal verification of pipelined processors with load-value prediction

    Publication Year: 2004, Page(s):41 - 46
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (651 KB) | HTML iconHTML

    The formal verification of pipelined processors with load-value prediction is studied. The formal verification is done by abstractions with the logic of equality with uninterpreted functions and memories (EUFM), using an automatic tool flow. Applying special abstractions in previous work had resulted in EUFM correctness formulas where most of the terms (abstract word-level values) appear in only p... View full abstract»

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  • Session 3: decision diagrams for verification

    Publication Year: 2004, Page(s): 47
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    Publication Year: 2004, Page(s): 48
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