Proceedings of 7th International Symposium on High-Level Synthesis

18-20 May 1994

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Displaying Results 1 - 25 of 27
  • An algorithm for the allocation of functional units from realistic RT component libraries

    Publication Year: 1994, Page(s):164 - 169
    Cited by:  Papers (6)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (554 KB)

    Existing algorithms in high-level synthesis (HLS) typically assume a direct mapping of hardware description language (HDL) operators to RT units. This assumption simplifies synthesis to generic RT components, but prevents effective use of complex databook components, custom designed cells, previously synthesized RT modules and RT module generators. We present an algorithm for allocation in HLS for... View full abstract»

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  • How datapath allocation affects controller delay

    Publication Year: 1994, Page(s):158 - 163
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (521 KB)

    We present an allocation approach which considers the controller's effect on system delay to minimize the system cycle time. Most allocation algorithms and conditional resource sharing methods emphasize minimum number of resources or area. Previous works have not modeled the resulting controller's structure and its contribution to the system delay in a controller/datapath system. The allocation me... View full abstract»

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  • Controller and datapath trade-offs in hierarchical RT-level synthesis

    Publication Year: 1994, Page(s):152 - 157
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (609 KB)

    We intend to study the impact of control logic on the RT-level design space of a class of digital system. Such an enhancement of the design space is more accurate than several previously reported approaches since control logic has a significant impact on the total cost and performance of the circuit. We present a datapath synthesis framework that is hierarchical in nature; and thus allows the cont... View full abstract»

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  • A specification invariant technique for operation cost minimisation in flow-graphs

    Publication Year: 1994, Page(s):146 - 151
    Cited by:  Papers (26)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (647 KB)

    In high-level synthesis, optimising area, time, and power in real-time applications are the prime objectives. A new model and technique are proposed, which minimise a weighted operation cost function for data-paths at an early stage in the synthesis process. The main target domain consists of lowly-multiplexed and hard-wired implementations of real-time DSP applications. The behavioral specificati... View full abstract»

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  • Global node reduction of linear systems using ratio analysis

    Publication Year: 1994, Page(s):140 - 145
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (518 KB)

    Linear systems are widely used in mathematics and engineering. Constructing a minimal directed acyclic graph (DAG) that corresponds to a given linear system is important in high-level synthesis. It is shown to be NP-complete. Ratio analysis, a novel multi-step algorithm for constructing a small sized DAG is presented. Ratio analysis attempts to minimize the total number of nodes in a DAG by maximi... View full abstract»

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  • Specification of interface components for synchronous data paths

    Publication Year: 1994, Page(s):134 - 139
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (494 KB)

    The simulation semantics of VHDL necessitates the specification of the interface signal transitions at bit level with exact timing which is not well suited for abstract specification and synthesis. The paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction levels are separated. It shows the transformations to genera... View full abstract»

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  • Rapid prototyping of fault tolerant VLSI systems

    Publication Year: 1994, Page(s):126 - 131
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (586 KB)

    We relate fault-tolerance constraints to chip area and present a methodology for rapidly compiling an algorithmic description into area-efficient fault-tolerant VLSI ICs. Whereas detection and recovery from environment induced transient faults is accomplished by checkpointing and rollback, uninterrupted operation for the lifetime of a mission is ensured by injecting redundancy. Towards validating ... View full abstract»

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  • A divide-and-conquer approach for asynchronous interface synthesis

    Publication Year: 1994, Page(s):118 - 125
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (869 KB)

    Asynchronous circuits are crucial in designing low power, high performance digital systems. They are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous interface circuits is a difficult and error-prone task. We present an area and time efficient synthesis algorithm for general signal transition graph (STG) specification... View full abstract»

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  • A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs

    Publication Year: 1994, Page(s):112 - 117
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (549 KB)

    We present an efficient and effective approach for checking synthesized RTL designs. This approach uses a hybrid numeric/symbolic simulation to extract the functional behavior of a design while taking into account the interaction between the data and control paths as well as the clocking scheme and delays, and employs a graph-comparison procedure to perform the checking task. The value of this wor... View full abstract»

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  • Testing two-phase transition signaling based self-timed circuits in a synthesis environment

    Publication Year: 1994, Page(s):104 - 111
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (693 KB)

    The problem of testing self-timed circuits generated by an automatic synthesis system is studied. Two-phase transition signaling is assumed and the circuits are targeted for an asynchronous macromodule based implementation. The partitioning of the circuits into control blocks, function blocks, and predicate (conditional) blocks, originally conceived for synthesis purposes, is found to be very eleg... View full abstract»

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  • Concurrent testing in high level synthesis

    Publication Year: 1994, Page(s):96 - 103
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (585 KB)

    For digital circuits synthesized from data-flow graphs, this paper presents a method to test the circuit concurrently with its normal operation. The method tests hardware elements when they are not in use in the data-flow graph. An algorithm for synthesizing the test circuit is presented that starts with the data-flow graph, generating a circuit to cycle test vectors through the idle hardware and ... View full abstract»

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  • Retargetable assembly code generation by bootstrapping

    Publication Year: 1994, Page(s):88 - 93
    Cited by:  Papers (4)  |  Patents (9)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (525 KB)

    In a hardware/software codesign environment compilers are needed that map software components of a partitioned system behavioral description onto a programmable processor. Since the processor structure is not static, but can repeatedly change during the design process, the compiler should be retargetable in order to avoid manual compiler adaption for each alternative architecture. A restriction of... View full abstract»

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  • Code generation for a DSP processor

    Publication Year: 1994, Page(s):82 - 87
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Proposes a method for compiling an application program into microcodes of a programmable DSP processor. Since most state-of-the-art DSP processors feature some sort of parallel processing architectures, the code generation is a non-trivial task. Based on several scheduling and allocation techniques previously developed by the CAD community for high-level synthesis, we propose a DSP code generator.... View full abstract»

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  • Bit-alignment for retargetable code generators

    Publication Year: 1994, Page(s):76 - 81
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (625 KB)

    When building a bit-true retargetable compiler, every signal type must be implemented exactly as specified, even when the word-length of the signal does not match the length of the available hardware. Extra operations must be introduced in the algorithmic description in order to ensure that the remaining bits do not influence the data-bits and to assure that signal types are correctly converted fr... View full abstract»

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  • An integrated approach to retargetable code generation

    Publication Year: 1994, Page(s):70 - 75
    Cited by:  Papers (22)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (513 KB)

    Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of registers, and highly specialized register capabilities. Many traditionally separate subproblems in code generation have been unified and jointly optimized within a single integer linear programming (ILP) model. ILP modeling provides a powerful methodology for generating... View full abstract»

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  • Ensemble representation and techniques for exact control-dependent scheduling

    Publication Year: 1994, Page(s):60 - 65
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (573 KB)

    Describes a new exact formulation of control/data-flow scheduling. Unlike current techniques, a closed form solution set is generated in which all satisfying schedules for arbitrary forward branching control/data paths and resource constraints are encapsulated in a compressed ordered binary decision diagram (OBDD) based representation. A robust, iterative construction strategy is presented along w... View full abstract»

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  • SMASH: a program for scheduling memory-intensive application-specific hardware

    Publication Year: 1994, Page(s):54 - 59
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (562 KB)

    Addresses automatic synthesis of memory-intensive application specific systems, with emphasis on hierarchical storage architecture design. SMASH is a program which combines storage hierarchy design with data path synthesis. It uses appropriate system parameters in order to coordinate between the synthesis of different subarchitectures of the system and schedules data transfers between them. We hav... View full abstract»

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  • Efficient timing constraint derivation for optimally retiming high speed processing units

    Publication Year: 1994, Page(s):48 - 53
    Cited by:  Papers (6)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Retiming, including pipelining, is applied to make the processing units (PUs) run at a required throughput rate with a minimum number of registers. In the first step, a timing analysis of a PU is performed which results in inequality constraints on the operations' retimings. The constraints, together with a cost function expressing the number of registers in a retimed PU, form an instance of an in... View full abstract»

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  • Timing estimation for behavioral descriptions

    Publication Year: 1994, Page(s):42 - 47
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (493 KB)

    Behavioral or high-level synthesis (HLS) generally produces a register transfer level (RTL) code which in turn is synthesized into a netlist. The RTL code that is generated by the HLS program needs to meet user constraints such as clock cycle, available function units, area, etc. This paper shows that most synthesis programs will not meet the user timing constraint in many cases. As a result, a ge... View full abstract»

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  • Computing lower bounds on functional units before scheduling

    Publication Year: 1994, Page(s):36 - 41
    Cited by:  Papers (11)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (610 KB)

    Presents a new algorithm for computing lower bounds on the number of functional units (FUs) required to schedule a data flow graph in a specified number of control steps. We use a formal approach to compute the bounds that can be proven to be tighter than those produced by existing methods, and that considers the interdependencies of the bounds on the different FU-types. This quick, yet accurate e... View full abstract»

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  • Applications of attributed-behavior synthesis

    Publication Year: 1994, Page(s):29 - 34
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (589 KB)

    Demonstrates some of the types of design problems that can be addressed using the attributed-behavior approach to high-level synthesis based design. In one example, assertions are used to enforce a template hierarchy in an effort to exploit data-flow regularity during high-level synthesis. In another, assertions are used to account for a probable effect of logic synthesis on register transfer leve... View full abstract»

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  • Timing analysis for synthesis in microprocessor interface design

    Publication Year: 1994, Page(s):23 - 28
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (609 KB)

    Design automation techniques are playing an important role in controlling the complexity of system design. The authors' work is inscribed in the design automation of microprocessor-based systems which necessitates the design of interfaces for system integration. During the interface synthesis it is required to validate the timing of a design yet to be implemented. In this paper they present a nove... View full abstract»

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  • Data routing: a paradigm for efficient data-path synthesis and code generation

    Publication Year: 1994, Page(s):17 - 22
    Cited by:  Papers (31)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Describes a new and effective approach to register and interconnect optimisation, which is applicable in a dual context: to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in retargetable code generation. The key idea is to carefully optimise the way in which data is transferred between functional units. The impact on high-level synthesis is demonstr... View full abstract»

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  • Instruction set definition and instruction selection for ASIPs

    Publication Year: 1994, Page(s):11 - 16
    Cited by:  Papers (50)  |  Patents (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (581 KB)

    Application Specific Instruction set Processors (ASIPs) are field or mask programmable processors of which the architecture and instruction set are optimised to a specific application domain. ASIPs offer a high degree of flexibility and are therefore increasingly being used in competitive markets like telecommunications. However, adequate CAD techniques for the design and programming of ASIPs are ... View full abstract»

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  • A methodology for simulation and synthesis of mixed hardware/software systems

    Publication Year: 1994
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (30 KB)

    Summary form only given. A methodology for designing embedded DSP systems containing interacting hardware and software components is presented. The software typically comprises a program running on a programmable digital signal processor and the hardware consists of the processor, custom synthesized hardware modules, and the interface between the two. The methodology allows the designer to begin w... View full abstract»

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