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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 2 • Date May 1995

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Displaying Results 1 - 25 of 27
  • Reliability issues of replacing solder with conductive adhesives in power modules

    Publication Year: 1995 , Page(s): 320 - 325
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    Electrically conductive adhesives are potential candidates as die attach materials for power modules because they offer simplified and environmentally compatible processing and easier reworkability compared to solder joining. There are, however, reliability issues which must be considered carefully before the adhesives can be used in a production setting. In this study, three silver-filled epoxy-based adhesives and a solder alloy were tested in a power module test structure. The test modules went through thermal and operational cycling as well as elevated humidity and temperature aging. Mechanical stresses were endured well by most of the test adhesives. Elevated humidity and temperature aging showed, though, that the right adhesive choice is important for successful module performance. One of the adhesives was clearly superior when compared with the other two adhesives. None of them, however, showed any silver migration in the humid conditions View full abstract»

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  • Evaluation of contact resistance for isotropic electrically conductive adhesives

    Publication Year: 1995 , Page(s): 299 - 304
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    Electrically conductive adhesives are discussed and studied with ever-increasing interest as an alternative to solder interconnection in microelectronics circuit packaging. A similar level of scrutiny that is used to evaluate contact resistance performance for interconnections made with solder and separable connectors is necessary for electrically conductive adhesives. Experience with solder interconnection and separable connectors shows low initial contact resistance of less than 10 mΩ when bulk conductor material is minimized in the measurement scheme. Stability is typically determined to be less than a 5-10 mΩ change as a function of stress. The main intent of this study is to characterize the electrical contact resistance performance of joints made with isotropic electrically conductive adhesives. A copper comb pattern test vehicle was designed and fabricated using 0.25-mm thick lead frame material. The plating finishes that were applied to the copper substrate included a palladium alloy, gold, tin, and nickel. Test samples were made with several electrically conductive adhesives. Samples consisted of two comb patterns bonded to each other making a gang of 40 lap joints. Variables from circuit packaging such as coefficient of thermal expansion mismatches are purposely avoided in this study. Contact resistance measurements were made initially and as a function of time during environmental tests. Stresses included thermal cycling, thermal aging, and temperature and humidity conditioning. The stability of electrical contact resistance is shown to be influenced by both plating metallurgy and the conductive adhesive itself. Contact resistance equivalent to solder is possible with some electrically conductive adhesives on appropriate metallurgical finishes. Mechanically, adhesive joints are less robust than solder joints, and therefore care must be taken to eliminate or minimize the effects of mechanical loading View full abstract»

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  • Electroless nickel/copper plating as a new bump metallization

    Publication Year: 1995 , Page(s): 334 - 338
    Cited by:  Papers (8)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    An electroless bumping method was developed both for flip chip and TAB applications. Electroless Ni/Cu plating is a maskless low-cost approach to bumping directly on aluminum bondpads. An immersion tin layer for coating and soldering is plated on the copper. Due to the high alkalinity (pH>12) of electroless Cu baths, a thick Ni layer of about 7 μm is required on the aluminum for seating. A shear strength of 180 cN and a contact resistance of less than 2 mΩ for the bumps were obtained. Because of the high hardness of nickel, conventional gang bonding techniques are not applicable. The hardness of electroless copper is about 200 mHV25, and after annealing in the range of 130-150 mHV25 thermocompression gang bonding of Au plated tape to the Ni/Cu/Sn metallization was carried out. The average pull strength was 50 cN. The influences of the size and electroless solder plating of the deposited copper are also investigated View full abstract»

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  • Performance, wireability, and cooling tradeoffs for planar and 3-D packaging architectures

    Publication Year: 1995 , Page(s): 339 - 345
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    Models for wiring length, cooling, wireability, and signal distribution are derived and integrated into a system-level performance metric used to compare packaging architectures for digital electronic systems. These include the common planar and stack-of-plane structures, in addition to fully 3-D structures with variable aspect ratios. This performance metric has been used to examine optimum packaging architectures for air and water-cooled systems as a function of a number of parameters including the total circuit count. The results show that none of these packaging architectures is always optimal. Rather, the optimum structure is determined by the specific set of system conditions chosen. The reader may easily use this model in order to determine the “best” packaging architecture for system parameters not included in this paper View full abstract»

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  • Low-cost molded packaging for optical data links

    Publication Year: 1995 , Page(s): 235 - 240
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    In order to lower the cost of optical data link packaging, a new technology has been developed which integrates optical and electrical components in a single, sealed, transfer molded package. This technology utilizes leadframes for low cost and mass handling. Overmolding is used for package sealing and optical port alignment. A unique process, two-step transfer molding, allows for internal shielding, intermediate IC testing, ease of assembly, and IC package sealing. An injection-molded outer housing is used for connector insertion and external shielding (through the use of conductive plastics). The first application of this technology is a high performance optical transceiver package for the growing FDDI market (125 Mb/s). With a duplex MIC connector, this package conforms to an industry standard outline and pinout. The optical transceiver easily meets full FDDI specifications. The design integrates an LED, PIN, transmitter IC, receiver IC, and two capacitors in a single, overmolded package. The final assembly sequence was conceived using the latest Design For Simplicity (DFS) principles. This paper describes the design concept and prototype model performance results View full abstract»

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  • Analysis of a multilayered-metal thin-film transmission line

    Publication Year: 1995 , Page(s): 381 - 387
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    In this study, a perturbed-TEM analysis was conducted on a two-wire transmission line with a two-layered metal system that represents a typical metallurgy used in thin-film multichip modules (MCM's). Closed-form solutions were obtained for the current density, resistance, inductance, attenuation, and phase velocity. The proximity effects were clearly illustrated in the current density plots. It was shown that the increase in the attenuation and the resistance was caused by the skin effect and the power loss in the cladding conductor (copper line clad with 0.1-μm thick chromium), and the increase (decrease) in the phase velocity (internal inductance) of the thin-film lines was caused by the penetration of the magnetic field into the conductors View full abstract»

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  • Development of conductive adhesive joining for surface-mounting electronics manufacturing

    Publication Year: 1995 , Page(s): 313 - 319
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB)  

    This paper presents the results of a study of process development for conductive adhesives as solder replacement. The main objective of the work was to investigate the potentials for using conventional surface-mounting equipment for component assembly with conductive adhesives. Two processes have been studied: one which uses both anisotropically and isotropically conductive adhesives and one which uses isotropically conductive adhesives only. The results from the work show that currently available surface-mounting machinery can be used for the conductive adhesive joining process. However, further work is needed to optimize the processing conditions. Transmission electron microscopy analysis of the adhesive joints after temperature cycling and humidity testing shows that oxide layer formation on metal surfaces can be one of the mechanisms which causes decrease in the electrical performance of the joint View full abstract»

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  • Low-loss intersecting grooved waveguides with low Δ for a self-holding optical matrix switch

    Publication Year: 1995 , Page(s): 241 - 244
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    Our method using low Δ waveguides decreases the insertion loss of intersecting optical waveguides with grooves. Theoretical analysis by the beam propagation method or the plane wave expansion method shows the benefit of decreasing the insertion loss. Experimental measurements on a trial matrix (21×21) showed that the transmission loss greatly decreased with decreasing Δ. The reflection loss was less sensitive to the positional deviation of the groove than that of conventional Δ waveguides. The experimental results were used to calculate the total insertion loss. It decreased from 5.72 to 3.28 dB, when Δ decreased from 0.31 to 0.15% for a matrix scale of 50×50 View full abstract»

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  • Laser-detector-hologram unit for thin optical pick-up head of a CD player

    Publication Year: 1995 , Page(s): 245 - 249
    Cited by:  Papers (4)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    A laser-detector-hologram (LDH) unit having the size of 4.8×8.2×1.3 mm for use as a thin optical pick-up head of a CD player has been successfully developed. The technology to make the LDH unit thin and small is based upon the following techniques: 1) an efficient optical combination of a low operating current laser diode and a 45° built-in micromirror which is formed on a Si photodetector substrate, 2) a thin plastic-molded flat package with good thermal dissipation, and 3) a plastic-molded holographic optical element (HOE) as a cap. The pick-up head with the LDH unit has shown good optical performance, which is sufficient for the application to CD players View full abstract»

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  • Reliability assessment of isotropically conductive adhesive joints in surface mount applications

    Publication Year: 1995 , Page(s): 305 - 312
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    A study of conductive adhesive joining technology on printed circuit boards (PCB) was conducted. Six different isotropically conductive, silver-loaded epoxies were evaluated for the surface mount process. These adhesives were used to attach electrically and mechanically 160-lead, 25-mil pitch, quad flat package (QFP) and 0805 chip components on PCB's with hash gold, passivated copper, and tin/lead metallization. The reliability of the conductive adhesive joints was evaluated in two types of environmental test: constant humidity at 60°C and 90% RH for 1000 h, and temperature cycling for 1000 h from -40°C to 85°C. Under these conditions, both the electrical performance, in terms of contact resistance and surface insulation resistance (SIR), and the mechanical strength of the adhesive bonds were evaluated. The results show that reliable conductive adhesive joining can be achieved for both chip components and QFP components on PCB's with all three metallizations tested. Under well-controlled conditions, and with the right choice of adhesive for the application in mind, no significant increase or variation in electrical resistance during the temperature cycling test was encountered. The humidity exposure test was found to have a minor impact on both contact resistance and adhesion strength of most adhesives tested. In general. There was little difference between the different PCB metallizations used (except for SIR measurements). No evidence of silver migration could be observed after the humidity exposure for any of the adhesives tested View full abstract»

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  • Performance and reliability of optical fiber connectors in the outside plant environment

    Publication Year: 1995 , Page(s): 221 - 226
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    Telecommunication (telco) systems for telephony, video, and other broadband services will use a large number of fiber optic connectors and many of these connectors may be deployed in the outside plant (OSP). To meet telco plant expectations, these connectors must maintain their performance for at least 15-20 years. Are the available fiber optic connector designs capable of meeting these requirements? Is there a concern about connector performance or reliability? To answer these questions and develop some understanding of the behavior of fiber optic connectors in the OSP environment, SC type connectors from four manufacturers were evaluated by subjecting them to a sequence of tests simulating OSP conditions. This paper presents the results of the environmental tests View full abstract»

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  • Inner lead gang-bonded devices with stacked Ni-Au bumps

    Publication Year: 1995 , Page(s): 366 - 374
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    Tape automated bonding (TAB) is a technique which is characterized by a small lead pitch, a small size, and a good high frequency behavior. To bond the inner leads of the TAB foil on the straight wall bumps on the integrated circuit (IC), thermocompression gang bonding is usually applied. If simple thin silicon nitride passivation layers are used, cracks are often observed in the sputtered TiW barrier layer (beneath the bump) and in the passivation layer of the IC. A theoretical model has been used to describe the deformation of the bump-lead structure. Comparison of this model with experimental results of the cracking behavior shows that both stress and strain at the bond pad-bump interface exceed the critical values for cracking. Plastic deformation at the bondpad is avoided if a two layer Ni-Au bump structure is used. While the plastic deformation required at the bond interface is kept constant, nickel layers with a thickness of at least 10 μm are required to avoid even the smallest cracks. If the gold layer thickness is at least 15 μm, the resulting bond strength is comparable with that of standard gold bumps. Deformation of the leads is restricted within acceptable limits, and the long-term reliability is not affected. Accelerated testing has been performed by high temperature storage, pressure cooker and air-to-air temperature shock testing View full abstract»

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  • Thick-film resistor/dielectric interactions in a low temperature co-fired ceramic package

    Publication Year: 1995 , Page(s): 346 - 352
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Various commercial thick-film resistors are processed with a low temperature co-fired ceramic (LTCC) packaging material. The electrical properties and microstructure of the resistors are correlated. Three types of resistor/dielectric interfaces are observed. The interactions that occur between the resistor and the dielectric during the co-sintering process are affected by the physical and chemical properties of the glass phase of the resistor material. These interactions between the resistor and the dielectric are kinetically controlled by glass flow at the sintering temperature and thermodynamically driven by the activity gradients between components in the glass phases. The effect of these interactions on the sheet resistance and temperature coefficient of resistance of the resistor materials are discussed View full abstract»

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  • Mechanical and electrical evaluation of a bumped-substrate die-level burn-in carrier

    Publication Year: 1995 , Page(s): 264 - 268
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    A high-yield die supply has been identified as a key requirement for the viability of commercial multichip modules (MCM). The result of die or wafer level test and burn-in (beyond the level of historical wafer probe) to provide dice with performance and reliability levels equivalent to single chip packaged (SCP) dice is commonly called known good die (XGD). There are many proposed methods to obtain KGD, at varying levels of maturity, and with varying levels of cost, complexity, and potential impact on device performance and reliability. In this paper, we describe the mechanical and electrical evaluation of a temporary die-level burn-in carrier designed for use in providing KGD. Three device types are used in this evaluation to explore the limitations of the carrier system under evaluation: a 1 M DRAM, a 128 k×8 SRAM, and a 56-K gate ASIC. Die size, and bond pad count, size and pitch all impact the applicability of the carrier system under evaluation. Mechanical evaluations performed to date include measurements of critical carrier features such as bump height, die alignment structure placement, and bond pad damage caused by the carrier contacts. Electrical evaluations include continuity and electrical test performance at multiple temperatures View full abstract»

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  • Power cycling and stress variation in a multichip module

    Publication Year: 1995 , Page(s): 388 - 395
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    The effect of inelastic (creep and plastic) deformation of solder joints during power cycling of a specific multichip module is presented here. The utilized finite element technique allows one to account for the stress redistribution in the module as a function of time while the deformation/creep of the solder joints occur. It is shown that a nonuniform stress distribution exists in the module during power cycling, which affects and controls the inelastic deformation and fatigue life of solder joints. It is also shown that the choice of a suitable material and geometry for different components contained in the module plays a very important role in enhancing the fatigue life of solder joints View full abstract»

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  • C-4/CBGA comparison with other MLC single chip package alternatives

    Publication Year: 1995 , Page(s): 250 - 256
    Cited by:  Papers (5)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    Future applications, will require higher I/O counts, more densification, lower cost, and greater performance. This paper demonstrates why area-array based chip-to-substrate and substrate-to-card interconnections are strategic, particularly solder bump flip chips (SBFC or C-4) and ceramic ball or column grid arrays (CBGA/CCGA), respectively. That is, SBFC are capable of high pin counts coupled with high yields, performance, and reliability. Moreover, recently introduced CBGA/CCGA interconnections provide substantial benefits over standard pin grid array (PGA) packages. Also, CBGA/CCGA packages possess the highest density achievable at the card level when utilized in conjunction with SBFC-mounted die View full abstract»

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  • Latent open defect detection using phase-sensitive nonlinearity detection technique

    Publication Year: 1995 , Page(s): 358 - 365
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    Alternating and direct electric currents are applied through the metal interconnections in electronic packaging to detect potential electrical opens, such as line narrowings, notches, nicks, cracks, weak connections, and interface contaminations. Due to the nonlinear relationship between the voltage across and current through the metal conductor, distortion signals are generated by the defect region as well as the good conductor. The signal generated from a latent open defect can be detected by comparing the defect signal phase with the reference phase produced by the good conductor. Application of this technique to electronic packaging development and manufacturing can improve product reliability and reduce cost by early detection of latent open defects View full abstract»

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  • MCM-LD: large area processing using photosensitive-BCB

    Publication Year: 1995 , Page(s): 269 - 276
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    This paper demonstrates how laminate based printed-wiring-board technology (PWB) and thin film deposited dielectric technology (MCM-D) can be combined to form a low-cost solution for microelectronic interconnect schemes which require high density circuitry. A multilayer telecommunications module was fabricated to demonstrate the feasibility of this MCM-LD concept. Standard copper-clad laminates were processed using conventional PWB techniques to form the first level of metal interconnects (75 μm lines and spaces). A photosensitive benzocyclobutene layer was coated onto the boards and patterned to form 50 μm×200 μm nested vias down to the metal lines. A second metal interconnect layer was formed from a sputtered seed layer and plated up copper. Chip interconnection was carried out using gold wirebonding. Several large-area-processing (LAP) techniques were evaluated to determine the compatibility of the two interconnect technologies and to demonstrate the cost advantages of manufacturing large panels at high throughput levels. Spin coating, spray coating, meniscus coating, and extrusion coating were compared as dielectric deposition options and an in-line belt furnace was used to cure the dielectric layers on the laminate boards (rapid thermal curing). Laminate materials which were evaluated include: FR-4 (epoxy), BT (bismaleimide-triazine), PI (polyimide), and CE (cyanate ester) View full abstract»

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  • Conductive adhesives for SMT and potential applications

    Publication Year: 1995 , Page(s): 284 - 291
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    Environmental issues have as ever-increasing influence on the selection of materials and processes in electronic manufacturing. This paper discusses the use of conductive adhesives as a replacement for solder on SMT-printed circuit boards. As a result of a world-wide market survey, a number of conductive adhesives have been selected. The key issue of this paper has been to uncover the market for adhesive types and their composition, as well as the technical investigation of the influence of component termination and printed-circuit surface types on adhesive bonding stability. Four different types of adhesives on two different metal surfaces are compared with conventional solder technology. Each adhesive has been applied to the PCB's by either screen printing or dispensing according to the manufacturer's recommendation, followed by curing. All PCB's went through thermal and humidity cycling followed by electrical measurements of resistance; all variants have been adhesion tested. All adhesive variants have been microsectioned for metallurgical and microstructure examination. Energy Dispersive Analysis of X-ray (EDAX) of the metal particles in the adhesive has been carried out and documented. Rework of conductive joints is briefly addressed. Finally, aspects of occupational health are discussed concerning work with adhesive types. Work with epoxy-based adhesives has been brought into special focus View full abstract»

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  • Modeling joining materials for microelectronics packaging

    Publication Year: 1995 , Page(s): 326 - 333
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    Modeling of solder-substrate interactions together with careful experimental work can provide a good basis for developing new materials such as conductive adhesives and Pb-free solders as well as fluxless soldering processes for microelectronics packaging. The modeling of the solder-substrate interactions will in effect lead to a rationalization of the trial and error methods commonly employed and hence minimize the number of experiments required. It provides useful information on the chemical reactions, stabilities of various microstructures and growth rates of reaction products during joining or in use of electronic devices. This is of particular importance in the case of small solder volumes, since the compositions and microstructures of solder alloys can be entirely altered by the solder-substrate reactions during the joining. As specific examples the solder-substrate reactions have been investigated in the Sn-Bi/Cu and Sn-Bi-Zn/Cu systems with and without adhesives. The solder-substrate-environment interactions under high purity reducing gases have been studied also with the meniscograph. The reduction of surface oxides, formation and the stability of the intermetallic layers, Cu3Sn and Cu6Sn5, and the growth of brittle Bi layer in the microjoints due to the change of the composition of the solder filler was studied both theoretically and experimentally. Moreover, an explanation concerning the strong dewetting effect of zinc-containing solders found experimentally is given. An emphasis was placed also on the solder-substrate-environment interaction by studying the effect of humidity on chemical stability of microjoints in an epoxy-based adhesive View full abstract»

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  • Reliable Au-Sn flip-chip bonding on flexible prints

    Publication Year: 1995 , Page(s): 257 - 263
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    Flip-chip bonding, with an AuSn metallization system, has been successfully introduced for the mounting of integrated circuits (IC's) on flexible polyimide prints. Since in most consumer electronics, and more specifically for hearing instruments, the usable volume is decreasing very rapidly, maximum miniaturization is achieved by using flip-chips. In order to avoid open circuits during reflow soldering of all other components, a high melting soldering process is required for the bonding of the IC's. An additional advantage of the AuSn process is that the bumps do not completely melt, and a certain stand-off height is guaranteed. The bumps are deposited on top of the band pads and are bonded to copper tracks on a polyimide foil. The required tin is either deposited on the bump or on the copper tracks. Both AuSn soldering processes are performed by using pulsed heat thermode (gang) bonding. It has been found that the quality of the bonds depends on the microstructure formed in the bonding region. Energy dispersed X-ray analysis (EDX) measurements indicate that eutectic (80/20) Au-Sn or ξ' phases are required for good quality bonds. To obtain these phases, the temperature at the interface and the initial amount of tin are optimized. As a consequence of a large thermal mismatch and a small stand-off height of the IC, the number of cycles to failure during temperature shock experiments is limited. The results are remarkably improved (by a factor of 20) by using an epoxy-based underfill material View full abstract»

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  • Fabrication of low loss polyimide optical waveguides using thin-film multichip module process technology

    Publication Year: 1995 , Page(s): 232 - 234
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    A simple, wet chemical patterning process for the fabrication of low loss waveguides using photosensitive polyimides is described. Optically transparent, fluorinated polyimides are modified by co-polymerizing a low concentration of photocrosslinking groups into the backbone. The polyimides can then be patterned into arrays of channels, ribs, or Y branches, by UV exposure through a photomask followed by wet chemical development. Sidewall smoothness and sidewall profiles can be controlled by varying exposure and development conditions. The resulting polyimide waveguides are low loss and can be coupled into an optical fiber by end-fire coupling. Results on channel guide coupling, propagation, and loss are described View full abstract»

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  • Electrically conductive adhesives: a prospective alternative for SMD soldering?

    Publication Year: 1995 , Page(s): 292 - 298
    Cited by:  Papers (32)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    Conductive adhesives offer a new prospective way for electrical connection of SMD components to printed circuit boards, because of their lower possible curing temperature, fine pitch capability, higher flexibility than solder, and process simplicity. However, the long-term behavior of conductive adhesive joints under various climatic conditions shows large variations with the type of adhesive and metallization used and needs further clarification. In this paper electrical and mechanical behavior of conductive adhesives are discussed for bonding R 1206 jumpers with SnPb or AgPd terminations on bare copper, SnPb or Au plated boards, both directly after bonding and after climate testing (damp heat, hot storage, and rapid change of temperature). The influence of the component terminations is found to be dominant. AgPd terminations show only small increase in contact resistance. Processing characteristics, shrinkage and moisture uptake for some of the adhesives also were determined View full abstract»

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  • Corrosion in plastic packages-sensitive initial delamination recognition

    Publication Year: 1995 , Page(s): 353 - 357
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    The interface between the molding compound (MC) and the chip surface is of considerable interest for failure analysis on plastic-packaged chips. Scanning acoustic microscopy (SAM) is widely used for nondestructive evaluation in this field. Prior research of stressed components has shown that some delaminations containing microbridges, or “spongy” elements, are undetectable by SAM. Corrosion proves to be a sensitive mechanism for detecting these failures. In certain cases corrosion can be detected quasinondestructively by IR microscopy, while conventional destructive physical analysis and optical microscopy remain the easiest way to assess it. Degradation of the interface molding compound and chip is detectable by SAM at a later stage View full abstract»

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  • Manufacturability of capacitively coupled multichip modules

    Publication Year: 1995 , Page(s): 277 - 281
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    Nearly all of the conductors interconnecting a die to a substrate can and should be replaced by capacitor junctions. Capacitive coupling is a new approach for mechanically and electrically packaging electronic modules, and provides order-of-magnitude decreases in manufacturing and repair costs, extremely tight junction pitch, lower power, higher speed, and much easier testing. In this paper, we review capacitive coupling and discuss novel issues of manufacturability and materials optimization for capacitively coupled electronic modules View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope