Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 4 • Date Nov. 1998

Filter Results

Displaying Results 1 - 23 of 23
  • Foreword - Microelectronics System Integration

    Publication Year: 1998 , Page(s): 322 - 323
    Save to Project icon | Request Permissions | PDF file iconPDF (60 KB)  
    Freely Available from IEEE
  • Foreword Contributions From The Sixth Topical Meeting On Electrical Performance Of Electronic Packaging

    Publication Year: 1998 , Page(s): 480
    Save to Project icon | Request Permissions | PDF file iconPDF (63 KB)  
    Freely Available from IEEE
  • 1998 Index IEEE Transactions on Components, Pack Aging, And Manufacturing Technology - Part B: Advanced Packaging Vol. 21

    Publication Year: 1998 , Page(s): 483 - 485
    Save to Project icon | Request Permissions | PDF file iconPDF (159 KB)  
    Freely Available from IEEE
  • Subject index

    Publication Year: 1998 , Page(s): 485 - 492
    Save to Project icon | Request Permissions | PDF file iconPDF (155 KB)  
    Freely Available from IEEE
  • Economics modeling of multichip module testing strategies

    Publication Year: 1998 , Page(s): 360 - 370
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply design for test (DFT) and built-in self test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We will analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental tradeoff analysis data generated for some leading-edge multichip designs will also be presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10-20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s). Hence, one has to be careful about generalizing the lessons learned from specific cases, since it could lead to nonoptimal solutions. A careful economic modeling of the various design, test and manufacturing parameters is clearly necessary for producing cost-effective high-quality products View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effective material properties and thermal stress analysis of epoxy molding compound in electronic packaging

    Publication Year: 1998 , Page(s): 413 - 421
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    In this study, the coefficient of thermal expansion (CTE) and the elastic modulus of epoxy molding compound (EMC) are measured using fabricated specimens and then the measured values are compared with the predicted values by theoretical equations (such as dilute suspension method, self consistent method, Hashin-Shtrikman's bounds, Shapery's bounds and others). The measured values are distributed within the upper and lower bounds of predicted values. The measured elastic modulus and the CTE of EMC approach close to the predicted values by self consistent method and upper bound of Shapery's equation respectively. Two-dimensional (2-D) and three-dimensional (3-D) finite element analysis are performed using the measured and analytically predicted values. Finite element method (FEM) analysis indicates that firstly the EMC with eighty weight percentage of filter shows less thermal stress when package is cooling down and relatively high thermal stress when package is heating up. Secondly the stress concentrations at the edge sections about two times higher than the interfaces and at the vertex parts about 1.4 times higher than the edge sections are observed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microstrip-to-microstrip interconnects with adhesive bonded ribbons for micro- and millimeterwave applications

    Publication Year: 1998 , Page(s): 463 - 470
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    A simple chip-to-chip interconnect technique with adhesive bonded ribbons is presented. It solves the insertion loss problem of wire bond interconnects in micro- and millimeterwave assemblies. The following paper discusses design and fabrication of such interconnects. A quasistatic model is developed to ease the quality assessment of their electrical behavior. It is validated by measurements on microstrip resonators with and without interconnects. The chip-to-chip interconnect technique with adhesive bonded ribbons exhibit low loss and is useable up to 50 GHz or more View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Polymeric conductive pastes as solder replacement for flip-chip attachment

    Publication Year: 1998 , Page(s): 382 - 393
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1204 KB)  

    The fabrication and characterization of flip-chip assemblies using four polymeric conductive pastes as attachment materials are reported. Three thermoset and one thermoplastic polymeric conductive pastes were investigated. Polymeric conductive pastes having silver particles 2 μm in size made good contact to either smooth or rough metal. Electrical contact with pastes whose particles were 5 μm or larger could only be obtained on rough metal View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-cost technique for reducing the simultaneous switching noise in sub-board packaging configurations

    Publication Year: 1998 , Page(s): 428 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1116 KB)  

    As an easy-to-maintain low-cost packaging system, a sub-board packaging configuration has been developed. However, the simultaneous switching noise tends to increase, because a large number of switching large scale integrations (LSIs) are integrated in a sub-board. A low-cost technique for reducing simultaneous switching noise in sub-boards has been developed. A thin insulator film made of conventional FR4 substrate material is used to reduce the frequency response in the power-supply planes of the sub-board at frequencies below about 600 MHz. The Vu peak-noise amplitude was reduced by about 50% when 32 switching gates in the sub-board were simultaneously driven at 622.08 Mb/s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solder-jetted eutectic PbSn bumps for flip-chip

    Publication Year: 1998 , Page(s): 371 - 381
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    The commonly used deposition technology for solder bumps (evaporation or electroplating) requires thin-film processing. The compatibility of the solder-wettable metallizations does not allow the use of the same production equipment as installed in the wafer-fabrication facility. In this study, a maskless bump process is described, Here, solder droplets are ejected from a capillary and impinge on wettable bond-pad metallizations of electroless-deposited Ni/P-Au. Droplets impinging on a rough surface layer often bounce away. It is shown that this roughness layer is mainly determined by the Zn nucleation on the bondpad metallizations. Nucleation conditions are optimized to deposit only small particles of the same size. The volume of the droplets depends on the product of pulse amplitude and pulse length. Degradation of the interconnection between the piezoelectric actuator and the glass capillary requires a larger pulse amplitude for stable jetting behavior. In addition, it is found that every first droplet on a new position is larger than all other droplets ejected directly thereafter. The diameter distribution of the latter are within the requirements for the final bump. The quality of the solder-jetted bump is studied by several reliability tests after flip-chip assembly on printed wiring boards (PWBs). In combination with underfill, the reliability of solder-jetted bumps are comparable with electroplated bumps View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Numerical stress analysis of resin cracking in LSI plastic packages under temperature cyclic loading. III. Material properties and package geometries

    Publication Year: 1998 , Page(s): 407 - 412
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    In our previous reports [see ibid., vols. 19/20, p, 593/176, 1996/1997], geometries of the delaminations which are most likely to lead to resin cracking in large scale integration (LSI) packages subjected to temperature cyclic loading were identified for both Cu alloy and alloy 42 leadframe packages. In this paper, assuming these delaminations, we conduct comprehensive numerical stress analysis of resin cracking to study the effect of properties of encapsulant resin and die-bonding materials and the package geometry factors. The impacts of these design parameters on resin cracking are determined and a package design guide is established View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Microfluidic MEMS for semiconductor processing

    Publication Year: 1998 , Page(s): 329 - 337
    Cited by:  Papers (6)  |  Patents (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    The advent of MEMS (microelectromechanical systems) will enable dramatic changes in semiconductor processing. MEMS-based devices offer opportunities to achieve higher performance and functionality, at lower cost, with decreased size and increased reliability. In this work, we describe the achievement of several important devices for use in the semiconductor equipment industry. They include a low-flow mass flow controller, a high-precision pressure regulator, and an integrated gas panel. Compared to current technology, the devices are ultra-small in size, thus minimizing dead volumes and gas contact surface areas. With wettable surfaces comprised of ceramic and silicon (or, silicon coated with Si3N4 or SiC), they are resistant to corrosion, and generate virtually no particles. The devices are created from modular components. The science and technology of these components will be detailed. The modules examined are: normally-open proportional valves; normally-closed, low leak-rate shut-off valves; critical orifices (to extract information of flow rate); flow models (to extract flow rate from pressure and temperature information); silicon-based pressure sensors; and, the precision ceramic-based packages which integrate these modules into useful devices for semiconductor processing. The work finishes with a detailed description of the low-flow mass flow controller View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interface reaction between Ag-Pd conductor and Pd-Sn solder

    Publication Year: 1998 , Page(s): 394 - 397
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    The intermetallic compound layer between Pb-Sn solder and Ag-Pd conductor after aging at 150°C has been studied; elemental and phase distributions of this layer has been probed using SEM, EPMA and EDX. The investigation of the microstructure of the layer with EPMA liner analysis reveals segregation of Ag-rich and Pd-rich phases. Quantitative EDX analysis results show that the Ag-rich phase contains Ag and Sn with the Ag/Sn ratio around 3/1, and the Pd-rich phase Pd and Sn with the Pd/Sn ratio around 1/4. These phases are confirmed to be the intermetallic compounds Ag3Sn and PdSn4, respectively View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dielectric constant and loss tangent measurement using a stripline fixture

    Publication Year: 1998 , Page(s): 441 - 446
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    A new approach to dielectric material characterization with a vector network analyzer is presented. As the characteristic impedance (Z 0) of a stripline transmission line can be accurately determined by measuring the two-port scattering parameters in the frequency range of interest, the dielectric constant of the insulation material that consists as part of the stripline configuration is then obtained by a relationship to the characteristic impedance. The dielectric loss (or loss tangent) can be determined by measuring the return loss and the insertion loss of the stripline. The validity of the technique is demonstrated for well-characterized dielectric materials such as Teflon-based and other composite laminates. The technique is then applied to integrated circuit (IC) molding compounds as-processed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 8-Bit 2-gigasample/second A/D converter multichip module for digital receiver demonstration on Navy AN/APS-145 E2-C Airborne Early Warning Aircraft radar

    Publication Year: 1998 , Page(s): 447 - 462
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2484 KB)  

    This paper will discuss multichip module technology as it is applied to a prototype high performance direct digitizing channelized radar receiver system under development for the Navy's E2-C Airborne Early Warning Aircraft, which encompasses both analog signals at UHF frequencies and multigigahertz digital signals. Critical issues which arise in the design of such a system will be discussed, including thermal management, transmission line design, design of power and ground distribution systems, and analyses of voltage standing wave ratio and simultaneous switching noise. This paper will describe in detail the simulations and analyses which were undertaken during the development of the multichip module containing the analog-to-digital converter and demultiplexer for this system. Finally, test results from measurements of analog-to-digital converter performance at the full operating clock rates of the multichip module will be described, along with lessons learned for the design of subsequent generations of these high performance mixed signal systems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Programmable neural logic

    Publication Year: 1998 , Page(s): 346 - 351
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element. It presents the advantage of reducing the area of the layout from O(n2) to O(n), (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multidimensional VCSEL-array push/pull module fabricated using the self-alignment mounting technique

    Publication Year: 1998 , Page(s): 471 - 478
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    We have developed plastic-molded receptacle-lope vertical-cavity surface-emitting laser (VCSEL)-array modules directly push/pull connectable with the one-dimensional (1-D) conventional mechanically-transferable multifiber push-on (MPO) fiber connector and with a new two-dimensional (2-D) MPO-compatible fiber connector developed for this module. The VCSEL was mounted on the plastic-molded package using a highly precise completely alignment-free process using flip-chip solder bonding and ball-guide die bonding. These modules exhibit an optical coupling loss of 0.67±0.23 dB (efficiency: 85.8±2.93%) and a loss deviation of less than 0.26 dB for 100 matings with the fiber connector (MMF50). The modules were operated at a bit rate of 1 Gbps/ch without an isolator and showed floorless bit error rate (BER) performance at temperatures up to 70°C. At 1 Gbps/ch their optical sensitivity at a BER of 10-11 was -26.0 dBm±0.9 dB. These structures and techniques are applicable to high-density, high-throughput optical parallel interconnections and optical space-division switches View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Review and summary of a silicon micromachined gas chromatography system

    Publication Year: 1998 , Page(s): 324 - 328
    Cited by:  Papers (19)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 μI sample loop; a 0.9-m long, rectangular-shaped (300 μm width and 10 μm height) capillary column coated with a 0,2-μm thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-μm diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55-80°C). With a helium carrier gas and nitrogen diluent, a 10 μI sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8 ×105 Pa) ran be separated in less than 30 min View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Aging effects on shear fatigue life and shear strength of soldered thick film joints

    Publication Year: 1998 , Page(s): 398 - 406
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    The effects of tin diffusion, silver and palladium dispersion, and intermetallic compound growth on the shear fatigue of solder joints between thick film mixed bonded conductor Pd-Ag and solder 62Sn-36Pb-2Ag are investigated. Microstructural analysis reveals that the intermetallic compounds (IMC's) Pd3Sn2, Pd3 Sn, Pd2Sn, Pd3Sn2, PdSn, PdSn2, PdSn4, Ag5Sn, Ag3Sn, PbPd3, and Pb3Pd5 are formed after aging. X-ray dot maps demonstrate that the longer the aging time, the more serious the silver and palladium dispersion into the solder and the tin diffusion into the conductor. It is observed that the tin diffuses to the interface of the substrate/conductor after 120 h aging. Shear strength tests with different strain rate show that the adhesion strength decreases with prolongation of aging time. Shear cycling tests indicate that the fatigue lifetime of the solder joints depends on the diffusion depth of the silver and palladium, especially the tin diffusion into the thick film conductor. The above results mean that the more serious is the tin and silver interdiffusion, and the more IMC's are formed in the solder joint (effects which are the result of prolonged storage at high temperature or of long term operation in real SMT assemblies), the more sensitive is the solder joint to stress. Eventually fatigue failure of the joint may result. It is argued that volume change and increased brittleness caused by the intermetallic formation, and volume swelling of the conductor layer due to tin diffusion, are major factors in the decrease of fatigue lifetime and degradation of the shear strength of the solder joints View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear fracture mechanics analysis on growth of interfacial delamination in LSI plastic packages under temperature cyclic loading

    Publication Year: 1998 , Page(s): 422 - 427
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    A study is made of the tendency of growth of delamination between dissimilar materials occurring in large scale integration (LSI) plastic packages under temperature cyclic loading. Two groups of delamination growth processes are considered; one along the interface between the top surface of the die pad and the die-bonding layer, and the other along the interface between the bottom surface of the die pad and the encapsulant resin. In each group several different initial patterns of delaminations are assumed. Stress intensity factors and their mode ratios at the tips of growing delaminations are calculated by combining a thermoelastic finite element method for nonlinear contact problems and a linear interface fracture mechanics approach. The effects of geometries of delamination and leadframe materials on the tendency of delamination growth are clarified View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architecture, defect tolerance, and buffer design for a new ATM switch

    Publication Year: 1998 , Page(s): 338 - 345
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, as well as the associated queueing, are distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fourth link is used to connect either to an external port or to other basic modules at higher levels of the hierarchy. From a hardware implementation perspective, the simplicity of the architecture stems from the fact that each node in the switch consists of two small crossbar switches of low complexity, a buffer, and a controller. The hierarchial nature of the topology allows for modular growth of the switch. Further, the interconnection topology of the switch makes it suitable for three-dimensional (3-D) (stacked VLSI) implementation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Possibilities and limitations of IDDQ testing in submicron CMOS

    Publication Year: 1998 , Page(s): 352 - 359
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    IDDQ testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which escape other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effects of floating planes in three-dimensional packaging structures on simultaneous switching noise

    Publication Year: 1998 , Page(s): 434 - 440
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    The effects of floating conductors in three-dimensional (3-D) packaging structures are investigated. The simulations are based on a frequency-dependent integral equation formulation for the calculation of the magnetoquasistatic current distribution in complex interconnect structures. The calculated current distributions are used to develop an inductance/resistance equivalent circuit representation of the package that can be used as a subcircuit in SPICE for simultaneous switching noise calculations. The model is frequency dependent and captures the effect that multiple solid/meshed ground/power planes, pins, vias and traces have on overall package inductive performance. The impact of floating planes, such as a heat spreader under a ball grid array (BGA) structure, on the mutual inductances of the structure is demonstrated. The frequency dependence of the floating plane effects is examined also. The behavior of the induced eddy currents in the floating plane is investigated also, particularly in the vicinity of interconnect discontinuities. Switching noise results obtained using SPICE simulation and the generated inductance/resistance equivalent package models show the effects of floating planes on switching noise View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope