Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

6-8 Dec. 2004

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  • Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

    Publication Year: 2004
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  • Proceedings - 2004 IEEE International Conference on Field-Programmable Technology - Title Page

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  • Table of contents

    Publication Year: 2004, Page(s):xi - xiv
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  • Programming a hyper-programmable architecture for networked systems

    Publication Year: 2004, Page(s):1 - 8
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    Modern programmable logic devices have capabilities that are well suited for them to assume a central role in the holistic implementation of networked systems. We have devised a highly flexible soft platform architecture abstracted from such physical devices, which may be viewed as a particularly configurable and programmable type of network processor. In this paper, we discuss a programming model... View full abstract»

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  • Self-recovery experiments in extreme environments using a field programmable transistor array

    Publication Year: 2004, Page(s):9 - 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (494 KB) | HTML iconHTML

    Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. However, current technology can only ensure very limited lifetime in extreme environments. This paper describes novel experiments that allow adaptive i... View full abstract»

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  • Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes

    Publication Year: 2004, Page(s):17 - 24
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB) | HTML iconHTML

    This work describes a generalized decoder implementation for structured low-density parity check (LDPC) codes. The decoder features low logic consumption, efficient memory management, and full parameterization for reconfiguration. The goal is to provide a unified solution for fast evaluation of a broad class of structured LDPC codes utilizing the properties of field programmable gate arrays (FPGA)... View full abstract»

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  • Partial character decoding for improved regular expression matching in FPGAs

    Publication Year: 2004, Page(s):25 - 32
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (483 KB) | HTML iconHTML

    High-speed string pattern matching in hardware is required in many applications including network intrusion detection applications. Regular expressions are one method to implement such matching and are often built in FPGAs using non-deterministic finite automata (NFAs). To obtain high throughputs it is necessary to process many bytes in parallel. This paper extends the modular NFA construction met... View full abstract»

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  • Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

    Publication Year: 2004, Page(s):33 - 40
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    The ability of a compiler to exploit loop-level parallelism in a reconfigurable array is significantly affected by the amount of flexibility in the interconnect architecture. A less flexible interconnect will make it more difficult for the compiler to find efficient loop-level pipelined schedules, leading to reduced instruction throughput, and larger configuration bit storage area. In this paper, ... View full abstract»

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  • Directional and single-driver wires in FPGA interconnect

    Publication Year: 2004, Page(s):41 - 48
    Cited by:  Papers (92)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    Modern FPGA architectures from Altera and Xilinx have shifted away from allowing multiple drivers to connect to each interconnect wire. This work advocates the need for this shift to single-driver wiring by investigating the necessary architectural and circuit design changes. When single-driver wiring is used, area improves by 25%, delay improves by 9%, and area-delay improves by 32% compared to b... View full abstract»

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  • A greedy algorithm for tolerating defective crosspoints in nanoPLA design

    Publication Year: 2004, Page(s):49 - 56
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (569 KB) | HTML iconHTML

    Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic programmable logic arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design as this scale. We introduce a strategy for t... View full abstract»

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  • SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

    Publication Year: 2004, Page(s):57 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (511 KB) | HTML iconHTML

    This work discusses the technology mapping problem on hybrid field programmable architectures (HFPA). HFPAs are realized using a combination of lookup tables (LUTs) and programmable logic arrays (PLAs). HFPAs provide the designers with the advantages of both LUT-based field programmable gate arrays (FPGA) and PLAs. Specifically, the use of PLAs leads to reduced area in mapping the given circuit. D... View full abstract»

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  • Placement and routing for non-rectangular embedded programmable logic cores in SoC design

    Publication Year: 2004, Page(s):65 - 72
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB) | HTML iconHTML

    As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. In many cases, non-rectangular programmable logic cores are required, either to better... View full abstract»

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  • QuickRoute: a fast routing algorithm for pipelined architectures

    Publication Year: 2004, Page(s):73 - 80
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (635 KB) | HTML iconHTML

    As interconnect delays begin to dominate logic delays in large circuits, pipelined interconnects will be needed to achieve the highest performance. In FPGAs, this pipelining will be provided by the configurable interconnect architecture itself. This changes the routing problem substantially since the shortest path problem, which is at the core of any router, becomes NP-hard when latency constraint... View full abstract»

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  • An FPGA-based Othello endgame solver

    Publication Year: 2004, Page(s):81 - 88
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB) | HTML iconHTML

    A single chip FPGA-based Othello endgame solver is presented in This work. The solver includes all the hardware for move checking, disc flipping, move selection, board evaluation and alpha-beta pruning. On a Xilinx Virtex XCVW00E-6 device operating at 50 MHz, the chip can search 3.14 million Othello positions per second. The endgame chip achieves a speedup of 3.5 over an 800 MHz Pentium III machin... View full abstract»

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  • Real-time detection of line segments using the line Hough transform

    Publication Year: 2004, Page(s):89 - 96
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    We describe a compact circuit for real-time detection of line segments using the line Hough transform (LHT). The LHT is a technique to find out lines in an image. The LHT is robust to noises, but requires long computation time. The circuit calculates: (1) r and /spl theta/ of lines (r is the distance from the origin to a line and /spl theta/ is the angle of the line) by the LHT units in parallel; ... View full abstract»

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  • gNBX - reconfigurable hardware acceleration of self-organizing maps

    Publication Year: 2004, Page(s):97 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (545 KB) | HTML iconHTML

    In this work a new FPGA based hardware accelerator (gNBX) for self-organizing maps is introduced. New principles for hardware acceleration of self-organizing maps, which increase the degree of parallelity and therefore the acceleration gain was presented. Our technology independent design description can be mapped on application specific integrated circuits if very high performance is required, as... View full abstract»

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