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Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects

27-27 Aug. 2004

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  • HOT 12 Interconnects - Symposium on High Performance Interconnects [2004] - Cover

    Publication Year: 2004, Page(s): 0_1
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  • [Blank page]

    Publication Year: 2004, Page(s): 0_2
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  • 12th Annual IEEE Symposium on High Performance Interconnects [2004] - Cover

    Publication Year: 2004, Page(s): i
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  • [Breaker page]

    Publication Year: 2004, Page(s): ii
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  • Proceedings - 12th Annual IEEE Symposium on High Performance Interconnects [2004] - Title

    Publication Year: 2004, Page(s): iii
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  • Copyright

    Publication Year: 2004, Page(s): iv
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  • Table of contents HOT Interconnects 12

    Publication Year: 2004, Page(s):v - vi
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  • Message from the General Chairs

    Publication Year: 2004, Page(s): vii
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  • Message from the Program Chairs

    Publication Year: 2004, Page(s): viii
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  • Hot Interconnects 12 Committees

    Publication Year: 2004, Page(s): ix
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  • Program Committee

    Publication Year: 2004, Page(s): x
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  • [Breaker page]

    Publication Year: 2004, Page(s): xii
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  • Buffers: how we fell in love with them and why we need a divorce [Keynote 1]

    Publication Year: 2004, Page(s): 1
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (61 KB) | HTML iconHTML

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Virtualizing the Net - a strategy for enabling network innovation [Keynote 2]

    Publication Year: 2004, Page(s): 2
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (52 KB) | HTML iconHTML

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • What are the future trends in high-performance inter.connects for parallel computers? [Panel 1]

    Publication Year: 2004, Page(s): 3
    Cited by:  Papers (3)
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  • Network processors: prospects for practical deployment [Panel 2]

    Publication Year: 2004, Page(s): 4
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  • Session 1: System Level Interconnects

    Publication Year: 2004, Page(s): 5
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  • Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects

    Publication Year: 2004
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  • Performance evaluation of InfiniBand with PCI Express

    Publication Year: 2004, Page(s):13 - 19
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (466 KB) | HTML iconHTML

    We present an initial performance evaluation of InfiniBand HCAs (host channel adapters) from Mellanox with PCI Express interfaces. We compare the performance with HCAs using PCI-X interfaces. Our results show that InfiniBand HCAs with PCI Express can achieve significant performance benefits. Compared with HCAs using 64 bit/133 MHz PCI-X interfaces, they can achieve 20%-30% lower latency for small ... View full abstract»

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  • Performance evaluation of the Cray X1 distributed shared memory architecture

    Publication Year: 2004, Page(s):20 - 25
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (493 KB) | HTML iconHTML

    The Cray X1 supercomputer is a distributed shared memory vector multiprocessor, scalable to 4096 processors and up to 65 terabytes of memory. The X1's hierarchical design uses the basic building block of the multi-streaming processor (MSP), which is capable of 12.8 GF/s for 64-bit operations. The distributed shared memory (DSM) of the X1 presents a 64-bit global address space that is directly addr... View full abstract»

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  • [Breaker page]

    Publication Year: 2004, Page(s): 26
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  • Session 2: Packet Classification And Lookup

    Publication Year: 2004, Page(s): 27
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  • Efficient multi-match packet classification with TCAM

    Publication Year: 2004, Page(s):28 - 34
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (546 KB) | HTML iconHTML

    Today's packet classification systems are designed to provide the highest priority matching result, e.g., the longest prefix match, even if a packet matches multiple classification rules. However, new network applications, such as intrusion detection systems, require information about all the matching results. We call this the multi-match classification problem. In several complex network applicat... View full abstract»

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  • Non-random generator for IPv6 tables

    Publication Year: 2004, Page(s):35 - 40
    Cited by:  Papers (24)  |  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (454 KB) | HTML iconHTML

    The next generation Internet Protocol, IPv6, has attracted growing attention. The characteristics of future IPv6 routing tables play a key role in router architecture and network design. In order to design and analyze efficient and scalable IP lookup algorithms for IPv6, IPv6 routing tables are needed. Analysis of existing IPv4 tables shows that there is an underlying structure that differs greatl... View full abstract»

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  • Efficient prefix cache for network processors

    Publication Year: 2004, Page(s):41 - 46
    Cited by:  Papers (21)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (478 KB) | HTML iconHTML

    Conventional routing cache systems store destination IP addresses in their cache directory. We present a routing cache technique that stores the most recently used route prefixes, instead of IP addresses, to achieve a significantly smaller cache size. A nesting prefix is partially represented in this cache by its minimal expansions. Such expanded prefixes are obtained using an incremental techniqu... View full abstract»

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