International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004.

8-10 Sept. 2004

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  • International Conference on Hardware/Software Codesign and Systems Synthesis (IEEE Cat. No.04TH8785)

    Publication Year: 2004
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  • [Breaker page]

    Publication Year: 2004, Page(s): 0_2
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  • International Conference on Hardware/Software Codesign and System Synthesis

    Publication Year: 2004, Page(s): i
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  • Copyright page

    Publication Year: 2004, Page(s): ii
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  • Message from the chairs - Welcome to CODES+ISSS 2004!

    Publication Year: 2004, Page(s): iii
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  • [Breaker page]

    Publication Year: 2004, Page(s): iv
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  • Table of contents

    Publication Year: 2004, Page(s):v - viii
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  • CODES+ISSS'04 Organizing Committee

    Publication Year: 2004, Page(s):ix - x
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  • Technical Program Committee

    Publication Year: 2004, Page(s): xi
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  • 2003-2004 Steering Committee

    Publication Year: 2004, Page(s): xii
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  • Additional reviewers

    Publication Year: 2004, Page(s):xiii - xiv
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  • Future challenges in embedded systems

    Publication Year: 2004
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  • Organic computing - on the feasibility of controlled emergence

    Publication Year: 2004, Page(s):2 - 5
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    This work gives an introduction to the research area of organic computing and shows chances, opportunities and problems currently tackled by researchers. First the visions that lead to this research area are discussed briefly. It is shown that the notion of emergence, a central phenomenon in organic computing, is a typical bottom-up effect with the interesting property of generating order from ran... View full abstract»

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  • A loop accelerator for low power embedded VLIW processors

    Publication Year: 2004, Page(s):6 - 11
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (506 KB) | HTML iconHTML

    The high transistor density afforded by modern VLSI processes has enabled the design of embedded processors that use clustered execution units to deliver high levels of performance. However, delivering data to the execution resources in a timely manner remains a major problem that limits ILP. It is particularly significant for embedded systems where memory and power budgets are limited. A distribu... View full abstract»

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  • Dual-pipeline heterogeneous ASIP design

    Publication Year: 2004, Page(s):12 - 17
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (518 KB) | HTML iconHTML

    We demonstrate the feasibility of a dual pipeline application specific instruction set processor. We take a C program and create a target instruction set by compiling to a basic instruction set from which some instructions are merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a h... View full abstract»

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  • Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures

    Publication Year: 2004, Page(s):18 - 23
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (501 KB) | HTML iconHTML

    State-of-the-art architecture description languages have been successfully used to model application-specific programmable architectures limited to particular control schemes. We introduce a language and methodology that provide a framework for constructing and simulating a wider range of architectures. The framework exploits the fact that designers are often only concerned with data paths, not th... View full abstract»

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  • Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

    Publication Year: 2004, Page(s):24 - 29
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (488 KB) | HTML iconHTML

    This work concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph wit... View full abstract»

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  • Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

    Publication Year: 2004, Page(s):30 - 35
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (473 KB) | HTML iconHTML

    Reconfigurable architectures have become increasingly important in years. We present an approach to the problem of executing 3D graphics interactive applications onto these architectures. The hierarchical trees are usually implemented to reduce the data processed, thereby diminishing the execution time. We have developed a mapping scheme that parallelizes the tree execution onto a SIMD reconfigura... View full abstract»

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  • Detecting overflow detection

    Publication Year: 2004, Page(s):36 - 41
    Cited by:  Patents (21)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (426 KB) | HTML iconHTML

    Fixed-point saturating arithmetic is widely used in media and digital signal processing applications. A number of processor architectures provide instructions that implement saturating operations. However, standard high-level languages, such as ANSI C, provide no direct support for saturating arithmetic. Applications written in standard languages have to implement saturating operations in terms of... View full abstract»

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  • Memory accesses management during high level synthesis

    Publication Year: 2004, Page(s):42 - 47
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    We introduce an approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a strategy for implementing signals (ageing vectors). We formalize the maturing process and ... View full abstract»

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  • Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

    Publication Year: 2004, Page(s):48 - 53
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (482 KB) | HTML iconHTML

    We describe the MultiFlex multi-processor SoC programming environment, with the focus on two programming models: a distributed system object component (DSOC) message passing model, and a symmetrical multi-processing (SMP) model using shared memory. The MultiFlex tools map these models onto the StepNP multi-processor SoC platform, while making use of hardware accelerators for message passing and ta... View full abstract»

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  • Benchmark-based design strategies for single chip heterogeneous multiprocessors

    Publication Year: 2004, Page(s):54 - 59
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (554 KB) | HTML iconHTML

    Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs traditionally targeted by the design automation (DA) community, general purpose designs traditionally targeted by the computer architecture (CA) community, nor pure embedded designs traditionally targeted by the real-time (RT... View full abstract»

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  • Automatic synthesis of system on chip multiprocessor architectures for process networks

    Publication Year: 2004, Page(s):60 - 65
    Cited by:  Papers (12)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (524 KB) | HTML iconHTML

    We present an approach for automatic synthesis of system on chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our... View full abstract»

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  • Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

    Publication Year: 2004, Page(s):66 - 71
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (536 KB) | HTML iconHTML

    In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing th... View full abstract»

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  • Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?

    Publication Year: 2004, Page(s):72 - 73
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