2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

17-19 June 2004

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  • 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

    Publication Year: 2004
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  • [Blank page]

    Publication Year: 2004, Page(s): 0_2
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  • 2004 Symposium on VLSI Circuits. Digest of Technical Papers - Title

    Publication Year: 2004, Page(s): i
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  • Copyright

    Publication Year: 2004, Page(s): ii
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  • Foreword - Welcome to the 2004 Symposium on VLSI Circuits

    Publication Year: 2004, Page(s): iii
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  • Executive Committees

    Publication Year: 2004, Page(s): iv
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  • Technical Program Committees

    Publication Year: 2004, Page(s): v
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  • Table of contents

    Publication Year: 2004, Page(s):vi - xi
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  • 2004 VLSI Circuits Short Course Program

    Publication Year: 2004, Page(s): xii
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  • Session quick index

    Publication Year: 2004, Page(s): xiii
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  • [Breaker page]

    Publication Year: 2004, Page(s): xiv
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  • Session 1 - Plenary Session

    Publication Year: 2004, Page(s): 1
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  • Image processing chain in Digital Still Cameras

    Publication Year: 2004, Page(s):2 - 5
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    Nobody is perfect, neither are the components used in digital still cameras. Nevertheless the photographer wants to see the best quality image taken with his/her Digital Still Camera (DSC). Today the number crunching power of signal processors is high enough that many of the imperfections created by the lens and the image sensor can be easily corrected. For instance lens vignetting, defect pixels ... View full abstract»

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  • Semiconductor technologies support new generation hybrid car

    Publication Year: 2004, Page(s):6 - 9
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    Recently, in the automobile industry, more and more electronic devices have been installed on vehicles to cope with issues related to environment safety, and information. High performance, reliability, and the cost reduction are required for the semiconductor devices used as the core of an electronic system. This paper will focus on semiconductors developed for the "Prius" and progress of microcom... View full abstract»

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  • [Breaker page]

    Publication Year: 2004, Page(s): 10
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  • Session 2 - RF Subsystems

    Publication Year: 2004, Page(s): 11
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  • An integrated 17 GHz front-end for ISM/WLAN applications in 0.13 /spl mu/m CMOS

    Publication Year: 2004, Page(s):12 - 15
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB) | HTML iconHTML

    This paper presents an integrated front-end for ISM/WLAN applications at 17.3 GHz in 0.13 /spl mu/m standard CMOS. The front-end chip includes an inductive source-degenerated low noise amplifier (LNA), a transformer-based Gilbert-mixer, an intermediate frequency (IF) amplifier and a buffer for the local oscillator (LO) input. The integrated receiver front-end achieves a gain of 34.7 dB, a SSB nois... View full abstract»

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  • A 72mW CMOS 802.11a direct conversion receiver with 3.5dB NF and 200kHz 1/f noise corner

    Publication Year: 2004, Page(s):16 - 19
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (277 KB) | HTML iconHTML

    A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13 /spl mu/m CMOS process. The chip has an active area of 1.8mm/sup 2/ with the entire RF portion operated from 1.2V and the low frequency portion operated from 2.5V. Its key feature is a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner. M... View full abstract»

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  • An ultra-low power MEMS-based two-channel transceiver for wireless sensor networks

    Publication Year: 2004, Page(s):20 - 23
    Cited by:  Papers (38)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    This paper explores the design and implementation of a low-power two-channel transceiver using micromachined resonators. Wireless sensor networks require transceivers that are small, cheap, and power efficient. RF-MEMS resonators are utilized to accommodate these constraints. The prototype 1.9GHz transceiver, designed in 0.13 /spl mu/m CMOS, operates at 1.2V and consumes 3mA in receive mode and tr... View full abstract»

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  • An injection locked, RF powered, telemetry IC in 0.25 /spl mu/m CMOS

    Publication Year: 2004, Page(s):24 - 27
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    This wireless transponder recovers power and a reference clock from an incident RF signal and returns data on a 900MHz carrier. A multi-stage voltage multiplier/rectifier converts the received low power RF signal to a useful DC voltage and stores the energy on a storage capacitor. The injection locking technique facilitates power efficient generation of a low phase noise 900MHz internal clock from... View full abstract»

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  • [Breaker page]

    Publication Year: 2004, Page(s): 28
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  • Session 3 - Advanced High Data Rate DRAMs

    Publication Year: 2004, Page(s): 29
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  • Burst cycle data compression schemes for pre-fuse wafer-level test in large scale high-speed embedded DRAM

    Publication Year: 2004, Page(s):30 - 33
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    This paper describes two novel data compression schemes suitable for high density and high speed embedded DRAMs. The parallel compression serial readout scheme reduces bit-scan test times to one eighth. The parallel compression multiplexed readout scheme realizes high frequency at-speed tests even with low cost testers. Both can be used for pre-fuse wafer tests requiring redundancy calculations. T... View full abstract»

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  • A 128Mb multi port media DRAM with four independent 4Gb/s serial ports

    Publication Year: 2004, Page(s):34 - 35
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (155 KB) | HTML iconHTML

    This paper proposes a 128-Mb multimedia-specific DRAM having 4 independent 4Gbps serial ports, 16 independent banks, and 512b I/O bus. The core bandwidth of 51.2-Gbps is fully utilized by the four independent RX-TX 4-Gbps serial ports. The over-sampling clock/data recovery, boosted column select, and data-line redundancy schemes realize high-speed data path. It is fabricated using 1.8V, 0.10/spl m... View full abstract»

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  • A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

    Publication Year: 2004, Page(s):36 - 37
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (162 KB) | HTML iconHTML

    A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock loading and PLL with loop zero from voltage offset are used. An analytical equation for estimating the input capacitance of pad with ODT (On-Die Termin... View full abstract»

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