Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

11-11 Aug. 2004

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  • Proceedings of the 2004 International Symposium on Low Power Electronics and Design

    Publication Year: 2004, Page(s): 0_1
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  • [Blank page]

    Publication Year: 2004, Page(s): 0_2
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  • Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

    Publication Year: 2004
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  • Copyright page

    Publication Year: 2004, Page(s): ii
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  • Foreword ISLPED proceedings

    Publication Year: 2004, Page(s): iii
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  • Table of contents

    Publication Year: 2004, Page(s):iv - viii
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  • Executive Committee and Symposium Officers

    Publication Year: 2004, Page(s): ix
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  • Technical Program Committee

    Publication Year: 2004, Page(s): x
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  • ISLPED'04 additional reviewers

    Publication Year: 2004, Page(s): xi
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  • Why hot chips are no longer "cool"

    Publication Year: 2004
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  • Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation

    Publication Year: 2004, Page(s):2 - 7
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB) | HTML iconHTML

    Low-power circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are... View full abstract»

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  • Larger-than-V/sub dd/ forward body bias in sub-0.5V nanoscale CMOS

    Publication Year: 2004, Page(s):8 - 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (413 KB) | HTML iconHTML

    This paper examines the effectiveness of larger-than-V/sub dd/ forward body bias (FBB) in nanoscale bulk CMOS circuits where V/sub dd/ is expected to scale below 0.5V. Equal-to and larger-than V/sub dd/ FBB schemes offer unique advantages over conventional FBB such as simple design overhead and reverse body bias capability respectively. Compared to zero body bias, they improve process-variation im... View full abstract»

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  • Technology exploration for adaptive power and frequency scaling in 90nm CMOS

    Publication Year: 2004, Page(s):14 - 19
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (401 KB) | HTML iconHTML

    In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modem deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Mea... View full abstract»

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  • Experimental measurement of a novel power gating structure with intermediate power saving mode

    Publication Year: 2004, Page(s):20 - 25
    Cited by:  Papers (37)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB) | HTML iconHTML

    A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 /spl mu/m CMOS bulk technology. Our measurement results show that the additional intermediate power-mode all... View full abstract»

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  • Improved clock-gating through transparent pipelining

    Publication Year: 2004, Page(s):26 - 31
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accu... View full abstract»

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  • Microarchitectural techniques for power gating of execution units

    Publication Year: 2004, Page(s):32 - 37
    Cited by:  Papers (117)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (489 KB) | HTML iconHTML

    Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then... View full abstract»

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  • SEPAS: A highly accurate energy-efficient branch predictor

    Publication Year: 2004, Page(s):38 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (531 KB) | HTML iconHTML

    Designers have invested much effort in developing accurate branch predictors with short learning periods. Such techniques rely on exploiting complex and relatively large structures. Although exploiting such structures is necessary to achieve high accuracy and fast learning, once the short learning phase is over, a simple structure can efficiently predict the branch outcome for the majority of bran... View full abstract»

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  • Understanding the energy efficiency of simultaneous multithreading

    Publication Year: 2004, Page(s):44 - 49
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of critical importance, and we present modeling extensions to an architectural simulator to allow us to study the power-performance efficiency of S... View full abstract»

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  • Impact of technology scaling on energy aware execution cache-based microarchitectures

    Publication Year: 2004, Page(s):50 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB) | HTML iconHTML

    Reducing total power consumption in high performance microprocessors can be achieved by limiting the amount of logic involved in decoding, scheduling and executing each instruction. One of the solutions to this problem involves the use of a microarchitecture based on an Execution Cache (EC) whose role is to cache already done work for later reuse. In this paper, we explore the design space for suc... View full abstract»

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  • Single-V/sub DD/ and single-V/sub T/ super-drowsy techniques for low-leakage high-performance instruction caches

    Publication Year: 2004, Page(s):54 - 57
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB) | HTML iconHTML

    In this paper, we present a circuit technique that supports a super-drowsy mode with a single-V/sub DD/. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as air al... View full abstract»

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  • Design and implementation of correlating caches

    Publication Year: 2004, Page(s):58 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB) | HTML iconHTML

    We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. In other words, if load X and load Y are two consecutively executed load instructions, the offset between the source addresses of these instructions... View full abstract»

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  • Dynamic power management for streaming data

    Publication Year: 2004, Page(s):62 - 65
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    This paper presents a method that uses data buffers to smoothen request variations and to create long idleness for power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes and the amount of data to store in the buffers. We use video prefetching as a ... View full abstract»

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  • Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

    Publication Year: 2004, Page(s):66 - 69
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50% reduction in energy dissipation. This observa... View full abstract»

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  • Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

    Publication Year: 2004, Page(s):70 - 73
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB) | HTML iconHTML

    This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high supply voltage (high-Vdd) or a low supply voltage (low-Vdd). We carry out the clustering procedure with the guarantee that the delay of the circuit under the general delay model is optimal, and in the meantime, logic block... View full abstract»

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  • Creating a power-aware structured ASIC

    Publication Year: 2004, Page(s):74 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB) | HTML iconHTML

    In an attempt to enable the cost-effective production of low and mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques which present more physical and structural regularity. This paper presents circuits which provide powe... View full abstract»

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