4th IEEE International Workshop on System-on-Chip for Real-Time Applications

19-21 July 2004

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  • 4th IEEE International Workshop on System-on-Chip for Real-Time Applications

    Publication Year: 2004
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  • Proceedings 4th IEEE International Workshop on System-on-Chip for Real-Time Applications

    Publication Year: 2004, Page(s): i
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  • [Blank page]

    Publication Year: 2004, Page(s): ii
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  • Proceedings 4th IEEE International Workshop on System-on-Chip for Real-Time Applications

    Publication Year: 2004, Page(s): iii
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  • Copyright page

    Publication Year: 2004, Page(s): iv
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  • Table of contents

    Publication Year: 2004, Page(s):v - x
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  • Message from the Chairs

    Publication Year: 2004, Page(s): xi
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  • Program Committee

    Publication Year: 2004, Page(s): xii
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  • SoC integration challenges

    Publication Year: 2004, Page(s): 3
    Cited by:  Papers (2)
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  • Automated fixing of complex/process critical DRC violations in place and route systems using calibre in the synopsys/milkyway environment

    Publication Year: 2004, Page(s): 7
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  • Integrating a single physical verification tool for systems-on-chip designs

    Publication Year: 2004, Page(s): 7
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  • High-speed I/Os and PLLs for data communication applications

    Publication Year: 2004, Page(s):11 - 12
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  • Formal verification of digital circuits

    Publication Year: 2004, Page(s): 15
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  • Silicon modeling of nanometer systems-on-chip

    Publication Year: 2004, Page(s):19 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (317 KB) | HTML iconHTML

    Given that more than half of mixed signal designs are failing first silicon, SoC designs require a comprehensive approach to parasitic extraction that satisfies the needs for accuracy, performance and detailed analysis. Parasitic extraction tools need to provide not only comprehensive evidence of unintentional parasitic effects, but also accurate data for accurate analysis. These analysis requirem... View full abstract»

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  • Beyond P-cell and gate-level: accuracy requirements for simulation of nanometer SoC design

    Publication Year: 2004, Page(s):23 - 26
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB) | HTML iconHTML

    The forward march of Moore's law has resulted in integrated circuit (IC) design containing more and more functionality on a single chip. While nanometer technology enables expanded capability, such as analog-mixed signal system-on-chip (AMS SoC), it brings with it a new set of design closure problems. Complex designs demand more power and higher clock frequencies; they also create more signal and ... View full abstract»

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  • A real-time architecture of SOC selective gas sensor array using KNN based on the dynamic slope and the steady state response

    Publication Year: 2004, Page(s):29 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB) | HTML iconHTML

    This paper demonstrates that using the dynamic response together with the steady state response greatly improves the classification performance of gas sensors. We propose a SOC VLSI architecture based on the KNN algorithm and operating on both the steady state and dynamic slope response of the data from the gas sensor array. The architecture is based on a current model analog pipelining strategy w... View full abstract»

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  • A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

    Publication Year: 2004, Page(s):33 - 36
    Cited by:  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB) | HTML iconHTML

    In this paper a CMOS image sensor with on-pixel analog-to-digital converter based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel form 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated... View full abstract»

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  • Interface-based design of systems-on-chip using UML-RT

    Publication Year: 2004, Page(s):39 - 44
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    While the IC industry tries to harness system-on-chip complexity by reusing intellectual property modules, practical problems abound, reusing within tight hardware constraints is a design journey that may cost more than building from scratch. Platforms using pre-characterized interfaces gained acceptance as a paradigm that increases reuse predictability. In this paper, we present an interface-base... View full abstract»

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  • Using design patterns for type unification and introspection in SystemC

    Publication Year: 2004, Page(s):45 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    Reflective environments such as .NET have provided programmers with the ability to gain access to a program structural information with ease. Reflectivity allows program metadata to be accessible at runtime. C++ is perceived by many to be a well-balanced language; it combines elegant software constructs and raw execution speed. Due to C++ success, many hardware engineers are moving away for tradit... View full abstract»

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  • A framework for implementing reusable digital signal processing modules

    Publication Year: 2004, Page(s):51 - 54
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (345 KB) | HTML iconHTML

    A framework for implementing reusable digital signal processing modules is presented. Based on a cellular structure, it offers a high level of configurability. With its predefined control strategy, and its generic architecture, the framework allows a fast and efficient implementation of digital signal processing applications. As a practical example, the implementation of a frequency estimator, cal... View full abstract»

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  • An optimal charge balancing model for fast distributed SystemC simulation in IP/SoC design

    Publication Year: 2004, Page(s):55 - 58
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (550 KB) | HTML iconHTML

    In this paper, we present a novel systematic approach to resolve the problem of charge balancing to reduce the simulation time for distributed simulation models. Our model is based on an exact method and permits obtaining an optimal repartition of the SystemC modules constituting a SoC on several simulators in geographically distributed hosts, connected through a network (Internet, Intranet). The ... View full abstract»

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  • A programmable base MDLNS MAC with self-generated lookup table

    Publication Year: 2004, Page(s):61 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB) | HTML iconHTML

    This paper presents an new architecture for a programmable second base multi-dimensional logarithmic number system (MDLNS) multiply accumulator cell (MAC) using DRAM to store the conversion lookup table (LUT). It uses a direct mapping from nonbinary exponents to binary format with a more than 50% reduction in DRAM size compared to a recently reported architecture. With a simple modification of the... View full abstract»

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  • 64-bit hybrid dual-threshold voltage power-aware conditional carry adder design

    Publication Year: 2004, Page(s):65 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    A 64-bit hybrid dual-threshold conditional-carry adder for power-aware applications was presented. Components on critical paths use a low threshold voltage to accelerate the speed of operation. Other components use the normal threshold voltage to save power. This is attractive in implementing power-aware arithmetic systems. The proposed circuit has the lowest power-delay product and energy-delay p... View full abstract»

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  • FPGA implementation of fast radix 4 division algorithm

    Publication Year: 2004, Page(s):69 - 72
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of a fast radix 4 division algorithm (Srinivas and Parthi, 1994) for lookup table based FPGAs implementation. In this algorithm, the quotient digits are dete... View full abstract»

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  • CRT-based three-prime RSA with immunity against hardware fault attack

    Publication Year: 2004, Page(s):73 - 76
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (279 KB) | HTML iconHTML

    In this paper, we carry out the study of the Chinese remainder theorem based three-prime RSA cryptosystem. The hardware fault attack on three-prime RSA cryptosystem is analyzed and it is proven that the three-prime RSA is more difficult to be broken than two-prime RSA by the hardware fault attack. Then, Shamir's checking procedure is extended from two-prime to three-prime RSA to increase its immun... View full abstract»

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