IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • Feb. 2019

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Publication Year: 2019, Page(s):C1 - C4
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• IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2019, Page(s): C2
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• Editorial TVLSI Positioning—Continuing and Accelerating an Upward Trajectory

Publication Year: 2019, Page(s):253 - 280
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• Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

Publication Year: 2019, Page(s):281 - 293
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This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two ... View full abstract»

• CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Publication Year: 2019, Page(s):294 - 303
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A CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm2Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64- $\mu \text{W}$ quiescent power and oper... View full abstract»

• A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration

Publication Year: 2019, Page(s):304 - 315
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A novel defect-tolerant network of digital-to-analog converters (DACs) is presented in this paper. The architecture of this converter employs a single 2.5-V voltage reference and an unbalanced buffering technique to achieve a wide voltage range that extends from 864 mV to 2.538 V with an 8-bit resolution. The proposed converter incorporates a defect-tolerant architecture and is extremely compact, ... View full abstract»

• A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18- $\mu$ m CMOS

Publication Year: 2019, Page(s):316 - 325
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A new solution for an ultralow-voltage bulk-driven (BD) asynchronous delta–sigma modulator is described in this paper. While implemented in a standard 0.18- $\mu \text{m}$ CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with $V_{\mathrm{ DD}} = 0.3$ View full abstract»

• A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs

Publication Year: 2019, Page(s):326 - 336
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This paper proposes a 10-bit two-stage resistor string digital-to-analog converter (R-DAC) architecture with source followers to isolate parallel-connected resistor strings, with a dc-offset compensation scheme to compensate for the offset voltages of the source followers. To compensate for these offset voltages, another source follower is inserted in the feedback loop of the buffer amplifier. Two... View full abstract»

• Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI

Publication Year: 2019, Page(s):337 - 349
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Recent progress in continuous-time (CT) Delta–Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These cha... View full abstract»

• A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs

Publication Year: 2019, Page(s):350 - 363
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Multicast communication (one-to-many) is common in parallel architectures and emerging areas, such as neuromorphic computing. However, there is very limited research in supporting multicast in asynchronous networks-on-chip (NoCs). This paper proposes a new parallel multicast asynchronous NoC with a 2-D mesh topology. To the best of our knowledge, this is the first general-purpose asynchronous NoC ... View full abstract»

• Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration

Publication Year: 2019, Page(s):364 - 375
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Reconfigurable systems often require secret keys to encrypt and decrypt data. Applications requiring high security commonly generate keys based on physical unclonable functions (PUFs), circuits that use random manufacturing variations to produce secret keys that are unique to each device. Implementing PUFs on field-programmable gate arrays (FPGAs) is usually difficult, because the designer has lim... View full abstract»

• A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits

Publication Year: 2019, Page(s):376 - 386
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In this paper, we propose an algorithm to classify spurious transitions in the activity of a digital circuit as generated and propagated glitches during logic simulation. Using the activities obtained, we compute a criticality metric to identify the nets where glitch minimization techniques are likely to provide the maximum benefit. The proposed metric provides insight into which techniques are be... View full abstract»

• A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

Publication Year: 2019, Page(s):387 - 397
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In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose–Chaudhuri–Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately afte... View full abstract»

• Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang–Bang Digital PLL With Transport Delay Using Fokker–Planck Equations

Publication Year: 2019, Page(s):398 - 406
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In this paper, a second-order bang–bang digital phase-locked loop (BBPLL) with dominant random walk phase noise and transport delay is analyzed using Fokker–Plank equations. Explicit closed-form expressions are derived for the timing error probability distribution function, jitter variance, and power spectral density (psd). For the type-II BBPLL considered in this paper, the timing error distribut... View full abstract»

• Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

Publication Year: 2019, Page(s):407 - 415
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In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is provided with increased resilience to single-event... View full abstract»

• A Secure Integrity Checking System for Nanoelectronic Resistive RAM

Publication Year: 2019, Page(s):416 - 429
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Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data th... View full abstract»

• A 100-mV–2.5-V Burst Mode Constant on-Time- Controlled Battery Charger With 92% Peak Efficiency and Integrated FOCV Technique

Publication Year: 2019, Page(s):430 - 443
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In this paper, a burst mode constant ON-time-controlled, energy harvesting charger is presented. The proposed boost converter system uses the burst mode control to improve the efficiency by 11%, compared to the conventional single-mode energy transfer implementation with an ultralow-power input comparator. A technique to deduce an optimum inductor energizes time across the given input range, for w... View full abstract»

• Power Scheduling With Active $RC$ Power Grids

Publication Year: 2019, Page(s):444 - 457
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Power gating is widely used in large chip design as a way to manage the total power dissipation and avoid overheating. It works by turning OFF the power supply to circuit blocks that are not required to operate in certain operational modes. Many authors have studied the scheduling of chip workload to manage total power and temperature. But power gating also has an impact on the supply voltage leve... View full abstract»

• A New Cellular-Based Redundant TSV Structure for Clustered Faults

Publication Year: 2019, Page(s):458 - 467
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Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process, which greatly reduces the yield of 3-D-ICs. The basic method to repair faulty TSVs (FTSVs) is to transfer the signals on FTSVs through regular TSVs. Many redundant TSV (RTSV) structures have been proposed to repair u... View full abstract»

• Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines

Publication Year: 2019, Page(s):468 - 480
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Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect... View full abstract»

• Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector

Publication Year: 2019, Page(s):481 - 485
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This brief presents a time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an improved variance-based time-skew estimation technique, where we introduce a window detector (WD) based on a SAR ADC. It brings low hardware overhead and 104 times faster convergence speed when compared to the prior variance-based time-skew calibration. Postlayou... View full abstract»

• Error Detection and Correction in SRAM Emulated TCAMs

Publication Year: 2019, Page(s):486 - 490
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Ternary content addressable memories (TCAMs) are widely used in network devices to implement packet classification. They are used, for example, for packet forwarding, for security, and to implement software-defined networks (SDNs). TCAMs are commonly implemented as standalone devices or as an intellectual property block that is integrated on networking application-specific integrated circuits. On ... View full abstract»

• High-Entropy STT-MTJ-Based TRNG

Publication Year: 2019, Page(s):491 - 495
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Hardware true random number generators (TRNGs) yield random numbers from physical processes. Traditionally, such devices are based on statistically random events such as thermal noise or other quantum phenomena. In this brief, we propose a novel TRNG design using a spin-transfer torque magnetic tunnel junction (MTJ) device. Our solution exploits the stochastic nature of the MTJ switching, and the ... View full abstract»

• Test Compaction by Test Removal Under Transparent Scan

Publication Year: 2019, Page(s):496 - 500
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This brief describes a new approach to test compaction under transparent scan. Transparent scan achieves higher levels of test compaction than possible with the conventional scan-based tests by interleaving scan shift cycles and functional clock cycles in arbitrary ways. Earlier approaches relied on the computation of a single transparent-scan sequence, and the omission of test vectors from it. Ho... View full abstract»

• IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2019, Page(s): C3
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Massimo Alioto
Department of Electrical and Computer Engineering
National University of Singapore
Singapore, 117583
malioto@ieee.org  massimo.alioto@gmail.com

Associate Editor-in-Chief
Mircea Stan
Electrical and Computer Engineering
University of Virginia
Charlottesville, VA 22904 USA
mircea@virginia.edu