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Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date 4-6 May 2004

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Displaying Results 1 - 25 of 111
  • Operator headcount optimization through VLSI test process simulator with human factor

    Publication Year: 2004 , Page(s): 383 - 388
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (491 KB) |  | HTML iconHTML  

    We have tried to optimize operator headcounts in the final test process of a one-chip microcomputer using a VLSI test process simulator with human factor to reply to an employment issue of how many new workers should be hired. The assumed final test process of a one-chip micro-computer has nine test flows that consists of fourteen stages at most. We select tasks for change kit exchanges and machine troubles as those required for a learning process. We simulate the work performance of newly hired workers by using the hyperbolic function with three parameters as a functional model of individual learning. According to the work performance value, we divide the learning process into three stages. The learning process for each stage differs according to relationships with expert workers. Our implemented event-driven simulator includes both processing-related and cost-related parameters. Simulations for two years were carried out for about total 2,400 lots/month. Result suggests that the manufacturing manager should hire new workers so that the ratio between newly hired and expert workers is about 1:2. View full abstract»

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  • A method for controlling residual film stress in LPCVD polysilicon films for surface micromachined MEMS

    Publication Year: 2004 , Page(s): 399 - 403
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    As the micro-electro-mechanical machine (MEMS) industry is maturing, an increased array of product applications and devices are being introduced. As these devices are being developed new processes are required to control and attain the desired levels of polysilicon stress. In this work the relationship between polysilicon blanket residual stress and dopant concentration and anneal conditions are investigated. It was found that as the sheet resistance increased, the magnitude of the stress increased several orders of magnitude. Annealing the wafers for increased durations and multiple cycles lowered the level of stress observed while reducing the response to dopant concentration. The response was reduced by fifty percent for a time increase from 20 to 180 minutes. It is suggested that specific levels of stress are best attained with modifications to the dopant concentration for the required thermal cycles. The characterization performed allows for reduced learning cycles and cost in the development of new MEMS process flows to achieve first pass success for device specific requirements. View full abstract»

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  • Application of advanced macro defect inspection technology for MEMS processes

    Publication Year: 2004 , Page(s): 367 - 372
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB) |  | HTML iconHTML  

    We describe the application of the August NSX-105 macro defect inspection tool in finding a defect that caused yield loss in the sensor portion of ADI's surface micromachining process for accelerometers. The source of the defect actually causes defects in both the circuit and sensor areas of the die, but due to the different processing that each location sees, the appearances were very different. Our work to improve yield in the sensor portion of the process thus improved the circuit portion of the process as well. View full abstract»

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  • Yield learning using the defect reticle method

    Publication Year: 2004 , Page(s): 110 - 114
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (497 KB) |  | HTML iconHTML  

    In this paper we describe a technique called the defect reticle method and illustrate its application to semiconductor manufacture. This technique sheds light on many unknown and so far inaccessible relationships between defect types and yield loss. We discuss an excerpt of results from the first year of application of this method within Infineon. View full abstract»

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  • Advanced metrology tool for Si1-xGex characterization: Infrared Spectroscopic Ellipsometer (IRSE)

    Publication Year: 2004 , Page(s): 425 - 432
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    The ability to precisely determine epilayer thickness and Ge concentration in Si1-xGex is essential for calibrating growth processes and thus control film quality. Spectroscopic ellipsometry is a nondestructive optical technique and has advantages for in-line process monitoring over SIMS, TEM and other destructive techniques. With integrated UV-Vis-IR spectroscopic ellipsometer, not only epilayer thickness and Ge concentration can be obtained with the UV-Vis channel, but also dopant concentration with the IR channel. Therefore, an advanced SOPRA IRSE 300 metrology tool will be used to characterize Si1-xGex epilayers. The sub 50-nm Si1-xGex films were processed with LPCVD in an AMAT 5200 Centura platform. The precursors for Si1-xGex growth are SiH4 and GeH4. B2H6 was used as the p-type dopant source (B) for certain samples. CH3SiH3 was also utilized as a carbon source to minimize boron out diffusion. Five types of samples were prepared and characterized, which are (a) single Si1-xGex layer (Box), (b) Si1-xGex layer with Si cap, (c) Si1-xGex layer with graded Ge concentration, (d) Boron doped Si1-xGex layer and (e) carbon effect on both undoped and doped Si1-xGex epilayers. Uniformity for these samples was also examined, which is an essential measure for improving process performance and device yield. Finally, results from spectroscopic ellipsometry were compared with that from other technique such as XRD for thickness and %Ge. View full abstract»

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  • Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

    Publication Year: 2004 , Page(s): 61 - 65
    Cited by:  Papers (1)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool. View full abstract»

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  • Overlay metrology sampling capability analysis and implementation in manufacturing

    Publication Year: 2004 , Page(s): 208 - 212
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (367 KB)  

    This paper outlines a technique for determining the sampling capability ratio (Csk)for overlay metrology and the implementation into the manufacturing line. This technique is analogous to the traditionally used process capability ratio (Cpk) with modifications to account for the systematic nature of misalignment. Specifically, the Csk analysis is based only on historical data which was available for metrology skips, uses modeled systematic data, and uses a statistical analysis based on the lognormal distribution including confidence intervals, and normality checking. In addition, upgrades to the statistical process control (SPC) strategy in photolithography are outlined as well as a future upgrade to the current system known as adaptive sampling. View full abstract»

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  • Infrared spectroscopic ellipsometry in semiconductor manufacturing

    Publication Year: 2004 , Page(s): 176 - 180
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (363 KB) |  | HTML iconHTML  

    IR-SE metrology is an emerging technology in semiconductor production environment. Infineon Technologies SC300 started the first worldwide development activities for production applications. One application part of our IRSE development roadmap is shallow trench isolation (STI) monitoring. Depth below silicon, film thickness and STI profile are the parameters of interest. A set of wafers with different lines/spaces structures (1D gratings) was prepared. These structures were characterized with atomic force microscope (AFM) for reference data. Extensive IRSE mapping measurements were taken, for 2 different wafers orientations, 0° and 90°. Preliminary outcomes are: A clear form birefringency and sensitivity to trench depth and lines density. To take advantage of this sensitivity to gratings depth, 2 concepts based on effective medium theory (EMT) and rigorous coupled wave analysis (RCWA) method were implemented. Excellent correlation results to AFM are presented for EMT for high lines density and for RCWA for low and high lines density. View full abstract»

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  • Universal and mobile Messaging Framework M2A "Message to Anywhere" for semiconductor manufacturing

    Publication Year: 2004 , Page(s): 241 - 243
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    This paper presents a software prototype for an universal and mobile Messaging Framework M2A "Message to Anywhere". Access on actual process data is an essential necessity in industrial production. This is how today's semiconductor manufacturing is able to meet requirements as: 1. Faster changing processes with more and more reduced quantities. 2. Access on various kinds of data. 3. Configuration of production sites distributed worldwide. 4. Increase availability (max MTBF/min. MTTR). View full abstract»

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  • Production implementation of state-of-the-art electron beam inspection

    Publication Year: 2004 , Page(s): 344 - 347
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    Electron beam inspection (EBI), through the use of voltage contrast, is used extensively throughout the industry to identify in-line electrical failures. The inspection methodologies presented in this paper help us to understand and react to these buried yield detractors in a timely manner. The result is an increase in disposition efficiency and a decrease in mean time-to-detect. This paper will describe the implementation of a state-of-the-art EBI technology into 300 mm wafer manufacturing using the KLA-Tencor eS30 EBI tool. First, results will be shown to demonstrate sensitivity, throughput, and overall production worthiness. Next, we will describe the implementation of this technology into IBM's 300 mm production line. Finally, we will describe a case study that illustrates the value of this technique for monitoring electrical defectivity in volume production. View full abstract»

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  • Future semiconductor workforce preparation based on Learning by Doing using Microelectronics Teaching Factory at Arizona State University East

    Publication Year: 2004 , Page(s): 389 - 394
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB) |  | HTML iconHTML  

    The traditional practice of the semiconductor industry has been to provide in-house hands on training to their newly hired employees (includes operators, technicians and engineers) with basic skills. The Microelectronics Teaching Factory (MTF) at Arizona State University East (ASU East) has taken up the challenge to be of assistance to the Industry by providing work ready graduates who can make an economic contribution immediately after graduation leveraging the experience gained through learning by doing in the classroom. The education effort that is underway in the MTF is fully supported and guided by an active local Semiconductor Industry Advisory Board. In this paper, we describe the installation of a toxic gas monitor in the ASU East MTF clean room facility as an example of a typical student project that encompasses the philosophy of learning by doing. View full abstract»

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  • Using embedded objects for yield monitoring

    Publication Year: 2004 , Page(s): 124 - 128
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (414 KB) |  | HTML iconHTML  

    In this article, we describe the use of embedded objects, such as scan chains and RAMs, for yield learning and as defect monitors. We discuss why these objects are suitable for yield learning, and what needs to be done to use them as such. We close with a number of examples, showing the use of embedded chains to improve yield. View full abstract»

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  • A simulation study of dispatching rules and rework strategies in semiconductor manufacturing

    Publication Year: 2004 , Page(s): 325 - 329
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    Two major operational components of semiconductor fabs that effect fab productivity are dispatching rules and rework strategies. Although prior research has been conducted independently on these two issues, the hypothesis here is that the interrelationship between the dispatching rules and rework strategies has a significant effect on the productivity of the fab. Moreover, the goal is to determine which combination of widely-used dispatching rules and new and existing rework strategies results in the highest level of fab productivity. To test this hypothesis, a four-factor experiment is conducted to determine the effect of dispatching rules, rework strategies, fab types, and rework levels on key fab performance measures. Five dispatching rules are combined with three previously studied rework strategies and the first bottleneck strategy which is developed in this study. The treatment combinations are compared based on fab performance measures. View full abstract»

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  • Wafer current measurement for process monitoring

    Publication Year: 2004 , Page(s): 303 - 307
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (414 KB) |  | HTML iconHTML  

    Wafer Current Measurement (WCM) is an emerging technique for in-line process monitoring. A joint development project (JDP) has been conducted by Infineon (Memory Development Center) and Applied Materials (Process Diagnostics and Control Group). The main goal of this project was development of applications for the WCM technique in Fab environment and specifically for state of the art DRAM Infineon process. A new generation of SEM review tool with integrated FIB (Applied SEMVision G2 FIB Defect Analysis system) was used for this work. A challenging layer approached in this work was the DTMO (Deep Trench Mask Open) which serves as a hard mask for subsequent deep trench (DT) capacitor formation in a silicon substrate. The aspect ratio of the openings in the DTMO layer can be as high as 20:1. As a result of the aggressive aspect ratio and sub-100 nm CDs the only available techniques for evaluating DTMO under-etch and bottom CD violation are destructive analysis methods. After demonstrating basic WCM based detection capability for nitride residual layer detection as well as for BSG under-etch the DTMO was approached and correlation of WCM readings to bottom/nitride CDs (measured by DTMO cross-sectioning) was achieved. Currently, DTMO bottom CD can be precisely measured after DT etch only with unavoidable wafer scraping in case of CD violation. After showing of bottom CD sensitivity using WCM, etch chamber/tool matching feasibility was conducted. The motivation behind this is that chamber/tool matching is essential to shorten cycle time. Crucial yield limiting problems such as nitride/BSG under-etch as well as bottom CD violation for DTMO layer can be revealed by the WCM in-line rather than by cross-sectioning in failure analysis laboratory or DT mask wet etch followed by top CD measurement. In production environment the WCM technique is targeted for excursion control, early etch process drift warning, and potentially for closed loop process control in DTMO and other process areas. View full abstract»

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  • In-line monitoring coverage visualization

    Publication Year: 2004 , Page(s): 135 - 139
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    In-line monitoring (ILM) is frequently used in semiconductor manufacturing to identify tool faults quickly and to minimize the impact on yield. Due to the expense of ILM only a fraction of the lots processed can be inspected. In practice process engineers devise a sampling plan to select lots for inspection so that 1) the inspection coverage, defined as the proportion of tools included in the inspection sample, is roughly equal to the tool usage and 2) all tools are covered by the inspection sample. This paper describes a new graphical display of tool usage, inspection coverage, and coverage loss that enables process engineers to quickly identify problems with the sampling plan. The displays are a graphical representation of the manufacturing process between inspection steps that show tool usage, inspection coverage, and the difference between usage and coverage. View full abstract»

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  • Plasma-damage optimization of the liner-removal process for 300 mm 0.13 μm copper dual-damascene BEOL manufacturing

    Publication Year: 2004 , Page(s): 213 - 216
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (434 KB) |  | HTML iconHTML  

    In this paper, an approach for optimizing plasma-charging damage of liner-removal process for 300 mm copper dual-damascene BEOL manufacturing is described. A specially designed cathode was first used to screen the process parameter response on damage performance. Real-time monitoring of etcher parameters during the process provided fast feedback about any plasma transient instability. Implementation of match tune and load preset methodology further improved the plasma transient uniformity to ensure an acceptable plasma-damage performance window from antenna MOS transistor parametric test results. View full abstract»

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  • Damascene tungsten process for local interconnects with improved reliability performance

    Publication Year: 2004 , Page(s): 472 - 476
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    Improved functional reliability is demonstrated through implementation of a tungsten damascene process for creating local interconnects that results in a cleaner, more planar surface. Reduction in lateral shorts is posited as the driver for the substantial reduction in yield loss and failure following stress conditions. View full abstract»

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  • A data mining projects for solving low-yield situations of semiconductor manufacturing

    Publication Year: 2004 , Page(s): 129 - 134
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    With huge amount of semiconductor engineering data stored in database and versatile analytical charting and reporting in production and development, the CIM/MES/EDA systems in the most semiconductor manufacturing companies help users to analyze the collected data in order to achieve the goal of yield enhancement. However, the procedures of semiconductor manufacturing are sophisticated and the collected data among these procedures are thus becoming high-dimensional and huge. Currently, some statistical methods, such like K-W test, covariance analysis, regression analysis, etc., have been used to analyze the information summarized from EDA system, and thus generate too many indexes that can not be easily judged and assimilated by engineers. Besides, too many false alarms may be raised and lots of time is required to check the factuality among them. In order to deal with the large amount and high-dimensional data, the data mining technologies are thus used to solve such problems. In this paper, we would like to propose a data mining solution and describe the experiences applying such solutions for discovering the root causes of low-yield situations in a worldwide semiconductor manufacturing company. Also, the situation of applying such mining solution for manufacturing defects detection in semiconductor manufacturing domain will be reviewed. Finally, the architecture of a reasonable, reliable and flexible data mining system will be briefly described. View full abstract»

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  • Using effective wet etching technology to improve deep trench shape

    Publication Year: 2004 , Page(s): 244 - 246
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    For trench type DRAM the trench surface in the depth direction of the capacitor without expanding the capacitor size is a good method to fit the specification of the charge storage. This paper reports a wet etching technology for modifying trench shape of the DRAM capacitor to enhance effective capacitance surface area. The ammonium hydroxide-water based wet etching solution was preferred over other etchants in our study experiments. The tested samples dipped in about 0.57 wt.% NH4OH then rinsed by H2O in sequence showed that excellent shape modification of the DRAM capacitor deep trench can be achieved. View full abstract»

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  • A systems approach to automation education and training

    Publication Year: 2004 , Page(s): 395 - 398
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    American industry has reached the highest level of productivity in its history in recent months and much of this increase can be attributed to the increased reliance on automation in the workplace. Over the past several years Intel, MATEC, and SMC International Training have teamed up to produce a new approach to educating future workers in this new automated environment. This paper discusses how this program was developed and provides an insightful look at the elements of automation education that we feel are necessary for students who will compete successfully in this new job market and for workers who are currently employed in the industry. View full abstract»

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  • Using fluorescent labeling of bacteria instead of the Filter membrane culture method to monitor bacteria in semiconductor equipment

    Publication Year: 2004 , Page(s): 355 - 358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (353 KB) |  | HTML iconHTML  

    This paper describes the sampling methodology, the benefits and lessons learned converting a semiconductor fab's ultrapure water (UPW) bacteria testing procedure to a process with a faster turn-around time. The fab went from using a Filter membrane culture method (FMC) for monitoring the bacteria in the ultrapure water (UPW) of process equipment to using the fluorescent labeling method using laser scanning cytometry (LSC). The new procedure was as good or better than the previous procedure although at a slightly higher cost. Several examples illustrate its use in releasing newly installed equipment to production and in troubleshooting bacteria contamination problems. View full abstract»

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  • Method for calculating high-resolution wafer parameter profiles

    Publication Year: 2004 , Page(s): 119 - 123
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    This paper describes a method to use parametric or yield data from many different products and die sizes for generating highly detailed wafer profiles. These profiles have an improved signal to noise ratio and spatial resolution compared to traditional wafer maps. This technique takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns. Several potential applications of these profiles were discussed. View full abstract»

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  • Exploring the limits of high temperature thermal processing for advanced 8-inch power technology manufacturing

    Publication Year: 2004 , Page(s): 27 - 31
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    Power processes are a challenge for 8-inch production especially in thermal processing. The temperatures exceed those used in DRAM and LOGIC by far and make a detailed knowledge of the critical process limits and maximum temperatures mandatory. We describe the experimental evaluation of these limits and compare the results to theoretical models, for both horizontal and vertical furnace equipment. Bulk micro defects are shown to be a key factor for any thermal process. We investigate in detail the key parameters for the different process regimes of boat push/pull, ramping as well as the impact of different boat and furnace equipment. View full abstract»

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  • Applications for automated wafer backside inspection

    Publication Year: 2004 , Page(s): 148 - 152
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB) |  | HTML iconHTML  

    The ability of an automated laser light inspection system to screen for backside defects on silicon wafers with a variety of known visual inspection rejects from various wafer manufacturing steps was tested. The inspection tool was challenged to discriminate the defects from a variety of backside finishes commonly found on silicon wafers (polished, etched, and films). The impact of the studied defects on wafer quality and yield are discussed. We demonstrate that the unique detector and illumination design of the inspection tool offer a viable option to visual inspection. View full abstract»

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  • Effects of intra chip topography in back end of line processes on focus leveling control and process window degradation with high NA exposures

    Publication Year: 2004 , Page(s): 75 - 78
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (330 KB) |  | HTML iconHTML  

    Modern High NA exposure systems trade off process depth of focus for gains in image resolution. The ever increasing Lens NA and associated loss of process window put greater demands on focus and leveling control as well as product design in order to gain back process capability. Poor chip design combined with multi level Back End of Line structures can create local topographies that exceed the focus budget of a modern High NA lens. The impact of these complications can be a significantly narrowed process window and increased ACLV. Advanced multi-point focusing and die-by-die leveling methods attempt to gain back focus window lost due to increased lens NA and wafer topography. In this paper we correlate surface topography and chip design to focus and leveling problems. Step height differences between Kerf and product surfaces were measured using AFM. Leveling tilts and effect on DOF were evaluated using FEM methods. ASML leveling metrology methods such as Dynamic Leveling, Local Offset Profile, Static Local Leveling, Static Global Leveling, and the use of Fixed Leveling Offsets were evaluated with respect to improving process windows and ACLV. View full abstract»

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