# IEEE Transactions on Circuits and Systems II: Express Briefs

## Issue 2 • Feb. 2019

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## Filter Results

Displaying Results 1 - 25 of 35

Publication Year: 2019, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2019, Page(s): C2
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• Analog and Mixed Mode Circuits and Systems
• ### A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM

Publication Year: 2019, Page(s):157 - 161
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An ultra-low-voltage 8-phase bootstrap (BT) ring-voltage-controlled oscillator (RVCO) exhibiting an improved figure of merit up to 165.2 dBc/Hz is reported. Unlike the existing RVCOs that use single-ended BT inverters with conventional clocks, our RVCO benefits from the inherent non-overlapping clocks of pseudo-differential BT inverters to reduce the charge loss due to asynchronous charge-pump ope... View full abstract»

• ### On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration

Publication Year: 2019, Page(s):162 - 166
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A gain and offset-calibrated 3-state phase detector is proposed to accurately measure static phase difference. Forcing the phase detector to operate in two different modes provides the full-scalegain since the sum of the two results is ${2}{\pi }$ . Flipping the inputs and averaging the results cancels the offset. Proposed cir... View full abstract»

• ### Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time

Publication Year: 2019, Page(s):167 - 171
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This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier (EA) for system-on-chip core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source vol... View full abstract»

• ### Generalized Method of Analog Circuit Characteristic Function Analysis

Publication Year: 2019, Page(s):172 - 176
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A novel and simple method for calculation of poles in electrical systems has been presented, which enables us to obtain the characteristic function without any complex computations. To do this, the circuits have been decomposed to three basic networks; as will be discussed in the text and according to the networks, the characteristic equation will quickly be achieved. The main advantages of the pr... View full abstract»

• ### A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector

Publication Year: 2019, Page(s):177 - 181
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An injection-locked clock multiplier (ILCM) using a frequency calibrator is presented to tolerate the process, voltage, and temperature variations. By detecting the timing error between the delay cells of a voltage-controlled oscillator (VCO) with and without an injection pulse, the frequency calibrator adjusts the oscillation frequency of a VCO. It reduces the reference spur and improves the rms ... View full abstract»

• ### A 20-kHz~16-MHz Programmable-Bandwidth 4th Order Active Filter Using Gain-Boosted Opamp With Negative Resistance in 65-nm CMOS

Publication Year: 2019, Page(s):182 - 186
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This brief presents a 4th order 20-kHz~16-MHz programmable-bandwidth active RC filter. For high linearity performance, the gain-boosted opamp in the biquad adopts negative resistance in auxiliary amplifiers to achieve high-gain without requiring extra common-mode feedback amplflifier, thereby minimizing total current and design complexity. To further enhance the filter linearity, a source follower... View full abstract»

• ### A 9-Bit 10-MHz 28- $\mu$ W SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC

Publication Year: 2019, Page(s):187 - 191
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A successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates “tapered bit periods” to reduce power consumption by minimizing the digital-to-analog converter (DAC) timing overhead. Utilizing a variable delay line and the standard SAR logic, the proposed technique reduces power by downsizing the DAC drivers and digital logic without decreasing the sampling rate. A detaile... View full abstract»

• ### A $\Delta\Sigma$ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

Publication Year: 2019, Page(s):192 - 196
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A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic comp... View full abstract»

• ### A Highly Digital ADC With Enhanced Accuracy Using a Simple Ripple-Transferring Replica Pseudo PLL Technique

Publication Year: 2019, Page(s):197 - 201
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We present a simple ripple-transferring replica pseudo phase-locked loop (PLL) technique for a highly digital ADC. The ADC is mainly constituted by main and replica pseudo PLLs. Compared with conventional techniques, this technique minimizes the main loop’s input ripple by means of inverting the replica loop’s input ripple and transferring it to the input of the main loop for the sum of the two ri... View full abstract»

• ### A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique

Publication Year: 2019, Page(s):202 - 206
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A novel quadrature voltage-controlled oscillator (QVCO) featuring low power consumption is proposed in this brief. By utilizing the coupling current reuse technique, the coupling current of one core is shared as a source to bias the quadrature coupling device in the other core. Thus, the coupling current consumption is eliminated. Moreover, the injected tank current is reshaped to reduce noise inj... View full abstract»

• ### Design of a Tunable Anti-Aliasing Filter for Multistandard RF Subsampling GNSS Receivers

Publication Year: 2019, Page(s):207 - 211
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A novel reconfigurable dual-bandpass filter with independently controlled center frequencies and fixed bandwidths is presented. It was designed to be integrated as a radio frequency anti-aliasing filter in a reconfigurable multi-bandpass sampling global navigation satellite system (GNSS) receiver. The center frequency tuning ranges are 1190–1210 MHz and 1560–1590 MHz in the lower and the upper L-b... View full abstract»

• ### A Ka Band FMCW Transceiver Front-End With 2-GHz Bandwidth in 65-nm CMOS

Publication Year: 2019, Page(s):212 - 216
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A fully integrated Ka band frequency modulation continuous wave single-chip radar transceiver front-end is proposed in 65-nm CMOS technology. By utilizing VCO with multi-biasing varactor banks, the critical bandwidth and linearity have been improved. To address the challenges of losses and complexities in local oscillator (LO) distribution chain, a three-way transformer-based power divider is prop... View full abstract»

• Circuits and Systems for Communications
• ### Design of Reconfigurable Digital IF Filter With Low Complexity

Publication Year: 2019, Page(s):217 - 221
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Due to limited frequency resources, new services are being applied to the existing frequencies, and service providers are allocating some of the existing frequencies for newly enhanced mobile communications. Because of this frequency environment, repeater and base station systems for mobile communications are becoming more complicated, and frequency interference caused by multiple bands and servic... View full abstract»

• ### A Fully Digital Phase Modulator With a Highly Linear Phase Calibration Loop for Wideband Polar Transmitters

Publication Year: 2019, Page(s):222 - 226
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This brief presents a digital phase modulator for wideband polar transmitters. It adopts a digital-to-time converter (DTC) and a highly linear phase calibration loop that improves phase resolution for high data-rate systems. The proposed 10-bit DTC consists of a coarse 5-bit cascaded delay line and a fine 5-bit digitally controlled delay line. This DTC achieves a fine delay resolution with digital... View full abstract»

• ### A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing

Publication Year: 2019, Page(s):227 - 231
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Polar codes are a new class of forward-error-correction codes, which have been proved asymptotically capacity-achieving for symmetric memoryless channels. Successive-cancellation (SC) decoders are low complexity while suffering from low speed due to their serial processing nature. Based on a newly published fast simplified SC algorithm, we propose a more efficient decoder than the prior art in thi... View full abstract»

• ### A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

Publication Year: 2019, Page(s):232 - 236
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In this brief, we propose a hybrid phase locked loop (PLL) which employs a coarse resolution gated ring oscillator time-to-digital converter in the digital integral (I) path and a switched RC circuit in the analog proportional (P) path, which provide lower in-band noise than a bang-bang phase detector-based hybrid PLL (BB-HPLL). We also present noise analysis of the proposed PLL which shows that i... View full abstract»

• ### A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM

Publication Year: 2019, Page(s):237 - 241
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This brief reports a class-C mode-switching single-ended-complementary (MS-SEC) VCO for wideband operation. Unlike the existing wideband VCOs that utilize nMOS-only $-\text{g}_{\text{m}}$ transistors operating in the class-B mode to maximize the oscillation amplitude, our MS-SEC VCO combines the advantages of class-C mode, wh... View full abstract»

• Computer Aided Design and Electronic Design Automation
• ### Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

Publication Year: 2019, Page(s):242 - 246
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By increasing the number of cores on a chip in the past decade, the network-on-chip technology has been developed to address scalability issues that arise in highly demanded multi-core architectures. Nevertheless, interconnection networks impose additional hardware overhead such as: routers, network interfaces, and increased power consumption. Power-gating (PG) the idle components has been employe... View full abstract»

• Control Theory and Systems
• ### An Observer-Based Fixed-Time Consensus Control for Second-Order Multi-Agent Systems With Disturbances

Publication Year: 2019, Page(s):247 - 251
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This brief considers the fixed-time consensus problem of second-order multi-agent systems with disturbances. With the proposed observer, the state information can be exactly estimated through output information in fixed time with the effects of bounded disturbances, and the second-order multi-agent system can also reach consensus in fixed time without using any velocity information. Finally, a num... View full abstract»

• ### Generalized Lagrange Multiplier Method and KKT Conditions With an Application to Distributed Optimization

Publication Year: 2019, Page(s):252 - 256
Cited by:  Papers (1)
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The Lagrange multiplier method is widely used for solving constrained optimization problems. In this brief, the classic Lagrangians are generalized to a wider class of functions that satisfies the strong duality between primal and dual problems. Then the generalized Karush–Kuhn–Tucker conditions for this generalized Lagrange multiplier method are derived. This useful method has applications in opt... View full abstract»

• Power Systems and Electronic Circuits
• ### Photovoltaic Energy Harvester With Fractional Open-Circuit Voltage Based Maximum Power Point Tracking Circuit

Publication Year: 2019, Page(s):257 - 261
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A photovoltaic (PV) energy harvester is proposed, and it adopts the fractional open-circuit voltage method to track the maximal power point of PV cells. The proposed harvester was designed and fabricated by using a 0.18- ${\mu }\text{m}$ 1P6M mixed-signal process. The input voltage of the proposed harvester may range from 0.5 ... View full abstract»

• ### Averaged Small-Signal Model of PWM DC-DC Converters in CCM Including Switching Power Loss

Publication Year: 2019, Page(s):262 - 266
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This brief proposes an improved averaged small-signal model of pulse-width modulated dc-dc power converters operated in continuous-conduction mode, which includes a resistance that corresponds to the switching power loss. Through this model, the switching power loss can be incorporated into existing averaged small-signal dynamic models. The proposed approach is based on the principle of conservati... View full abstract»

• ### Physical Interpretations of Grid Voltage Full Feedforward for Grid-Tied Inverter

Publication Year: 2019, Page(s):267 - 271
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Influence on an injected current arising from grid voltage is a noticeable issue in the design of grid-tied inverter, especially under low control gain or low power command conditions. The grid voltage full feedforward strategy is a widely used strategy to solve this problem, whereas the physical meanings of the full feedforward items are unclear. In this brief, the full feedforward of the direct ... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org