# IEEE Transactions on Circuits and Systems II: Express Briefs

## Issue 4 • April 2018

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## Filter Results

Displaying Results 1 - 25 of 27

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems - II:Express Briefs publication information

Publication Year: 2018, Page(s): C2
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• Analog and Mixed Mode Circuits and Systems
• ### Design and Characterization of a 43.2-ps and PVT-Resilient TDC for Single-Photon Imaging Arrays

Publication Year: 2018, Page(s):411 - 415
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This brief describes the design and characterization of a ring oscillator-based time-to-digital converter (TDC) with down to 43.2 ps of time resolution and high tolerance to process, voltage and temperature variations. By employing a compact architecture, it is therefore suitable for inclusion in imaging arrays for time-stamping functions. The proposed TDC has been fabricated in a 0.13- View full abstract»

• ### An Amplified Offset Compensation Scheme and Its Application in a Track and Hold Circuit

Publication Year: 2018, Page(s):416 - 420
Cited by:  Papers (2)
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This brief proposes a fully differential track and hold circuit using a new dc offset compensation scheme. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test... View full abstract»

• ### A Fifth-Order Butterworth OTA-C LPF With Multiple-Output Differential-Input OTA for ECG Applications

Publication Year: 2018, Page(s):421 - 425
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This brief proposes a fifth-order Butterworth operational transconductance amplifier-C (OTA-C) low-pass filter (LPF) with multiple-output differential-input (MODI) OTA structure and metal–insulator–metal capacitors for electrocardiography applications. The current division technology is used as an alternative output pair to provide multiple outputs and achieve high linearity. This te... View full abstract»

• ### A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators

Publication Year: 2018, Page(s):426 - 430
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In this brief, we design a single-channel 5-bit 500-MS/s asynchronous digital slope analog-to-digital converter. It is implemented and simulated in SMIC 55-nm CMOS technology. The power supply is 1.2 V and the improved delay cells are used, which can shorten the delay time to 50 ps. In addition, a self-disabled continuous-time comparator is used to save power. A strong-arm comparator is used to re... View full abstract»

• ### Analysis and Design of Dual-Band Rectifier Using Novel Matching Network

Publication Year: 2018, Page(s):431 - 435
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In this brief, a compact dual-band impedance matching network is introduced and applied to the design of rectifying circuits. The matching network can work at two arbitrary frequencies with arbitrary complex impedance simultaneously. Theoretical analysis is carried out and the closed-form design formulas are derived. For validation, a dual-band rectifier working at 0.915 and 2.45 GHz is implemente... View full abstract»

• ### A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS

Publication Year: 2018, Page(s):436 - 440
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This brief presents a 32 Gb/s driver for a Mach–Zehnder modulator (MZM) and an electro-absorption modulator (EAM). A push–pull current-mode logic driver is chosen to achieve a better power efficiency and a large voltage swing. A double cascode with thin oxide transistors is employed to mitigate the over-voltage stress associated with a large output voltage swing. At the same time, sh... View full abstract»

• ### Enhanced Single-Stage Folded Cascode OTA Suitable for Large Capacitive Loads

Publication Year: 2018, Page(s):441 - 445
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An enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gain-bandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a ... View full abstract»

• ### EMI-Related Common-Mode (CM) Noise Analysis and Prediction of High-Speed Source-Series Terminated (SST) I/O Driver in System-on-Package (SOP)

Publication Year: 2018, Page(s):446 - 450
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This brief presents, for the first time, a comprehensive analysis and prediction of electromagnetic interference-related common-mode (CM) noise for a 20-Gb/s source-series terminated I/O driver in a 65-nm CMOS process. The novel methodology is proposed to systematically analyze and predict the CM noise of an output driver from various dependent parameters, including CMOS process corners, input sig... View full abstract»

• ### A New Electronically Fine Tunable Grounded Voltage Controlled Positive Resistor

Publication Year: 2018, Page(s):451 - 455
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A new grounded voltage controlled positive resistor (GVCPR) is proposed in this brief. The proposed GVCPR with a single control voltage is composed of only six MOS transistors operated in saturation region. It has the feature of fine tunability from about 770 ${Omega }$ to about 1370 View full abstract»

• ### Available Energy of Improper Lossy LLTIP One-Ports

Publication Year: 2018, Page(s):456 - 460
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A method for evaluating the available energy of the improper lossy linear lumped time-invariant passive one-ports of any order is proposed. The approach devised is indirect, in the sense that it is based on a suited variable substitution that reduces the analysis of the improper lossy one-ports to that of the proper ones. In particular, explicit formulae for the available energy of the second-orde... View full abstract»

• ### Dual-/Tri-Band Branch Line Couplers With High Power Division Isolation Using Coupled Lines

Publication Year: 2018, Page(s):461 - 465
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Two novel dual-/tri-band branch line couplers with high power division isolation using coupled lines are proposed in this brief. Two conventional couplers loaded with quarter-wavelength open/shorted coupled lines are adopted to realize the dual or triple bands. Each band has a high isolation due to the introduced transmission zeros. The center frequencies of the two planar couplers can be adjusted... View full abstract»

• ### Designing Protograph-Based LDPC Codes for Iterative Receivers on ${M}$ -ary DCSK Systems

Publication Year: 2018, Page(s):466 - 470
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In this brief, protograph-based low density parity check (P-LDPC) codes, which have simple structure and excellent error-correction capability, are designed for iterative receivers (IRs) on ${M}$ -ary differential chaos shift keying ( ${M}$ -ary DCSK) syste... View full abstract»

• ### Event-Triggered Composite Control of a Two Time Scale System

Publication Year: 2018, Page(s):471 - 475
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This brief proposes an event-triggered composite control of a two time scale system. A periodic sampling requirement is relaxed and both slow and fast states of the system decide independently when transmitting their current measurements based on a time-dependent triggering rule. The distinct feature of this scheme is that it does not require synchronized measurement updates of its slow and fast d... View full abstract»

• ### Observers Design for 2-D Positive Time-Delay Roesser Systems

Publication Year: 2018, Page(s):476 - 480
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The problem of designing positive observers for 2-D positive Roesser systems with delays is addressed in this brief. Specifically, the design of an extended Luenberger-type observer that generates a nonnegative asymptotic estimation of the state vector and a reduced-order functional state observer that is an asymptotic approximation of a given linear functional of the state vector is considered fo... View full abstract»

• ### Performance Improvement of a Boost LED Driver With High Voltage Gain for Edge-Lit LED Backlights

Publication Year: 2018, Page(s):481 - 485
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This brief proposes a new method for improving the performance of a dc/dc boost converter used as a light-emitting diode (LED) driver for edge-lit LED backlights. The proposed method uses a passive snubber circuit that consists of two capacitors, two diodes, and an inductor; it improves the power efficiency of the dc/dc boost converter at the high duty ratio of the main switch by providing zero-cu... View full abstract»

• ### A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM

Publication Year: 2018, Page(s):486 - 490
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3-D cross point phase change memory (PCM) is considered to be a leading 3-D technology for emerging nonvolatile memories. Besides planar parasitic elements, vertical parasitic elements will also delay the read operation in 3-D PCM. This brief concludes the five factors that affect the read operation in 3-D cross point PCM for the first time. A single-reference parasitic-matching sensing circuit is... View full abstract»

• ### Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction

Publication Year: 2018, Page(s):491 - 495
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Aggressive technology scaling has accelerated the susceptibility of CMOS devices to aging effects. Consequently, the speed of a path can degrade significantly over time; this results in delay faults. Dynamic reliability management schemes have been proposed to ensure an IC’s lifetime reliability. Such schemes are typically based on the use of aging sensors to predict a circuit’s fail... View full abstract»

• ### A Low-Power Hybrid Adaptive CORDIC

Publication Year: 2018, Page(s):496 - 500
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The purpose of this brief is to introduce a hybrid adaptive coordinate rotation digital computer (HA-CORDIC) implemented on 65-nm silicon on thin buried oxide technology. The supply voltage of HA-CORDIC ranges from 0.25 V to 1.2 V and the lowest energy in active mode and sleep mode are 2.4 pJ/cycle and 0.003 pJ/cycle, respectively. By changing body bias voltages, the leakage current can be reduced... View full abstract»

• ### A Fast Converging Normalization Unit for Stochastic Computing

Publication Year: 2018, Page(s):501 - 505
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Stochastic computing is a promising technology for low hardware cost and low power digital signal processing (DSP) systems. However, the quite slow convergence of stochastic normalization leads to low throughput of stochastic computing based DSP systems. In this brief, we propose a fast converging stochastic normalization unit based on joint probability tracking (JPT) method, which operates modifi... View full abstract»

• Nonlinear Circuits and Systems
• ### Analysis of 3-Level Bandpass Sigma-Delta Modulators With 2-Level Output

Publication Year: 2018, Page(s):506 - 510
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This brief analyzes a recently introduced, 2-level bandpass modulator incorporating 3-level lowpass ΣΔ modulators. While the combination of 3-level ΣΔ with 2-level output improves output signal-to-noise ratio (SNR) in a wideband sense, it also introduces nonlinear distortion in the 2-level output. In this brief, the nonlinear effects are modeled and a linearization tech... View full abstract»

• ### On the Super-Lorenz Chaotic Model for the Virtual Synchronous Generator

Publication Year: 2018, Page(s):511 - 515
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Distinguished from the previous virtual synchronous generator (VSG) using the power equation of the three-phase voltage-source inverter (VSI) as the swing equation, this brief considers a new VSG that utilizes the voltage equation of the dc-link capacitor of the three-phase VSI as the swing equation, which reflects directly the dynamics of the rotor of the synchronous generator compared to the pre... View full abstract»

• ### A Revisit to Strictly Passive FIR Filtering

Publication Year: 2018, Page(s):516 - 520
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This brief revisits the strictly passive finite impulse response (FIR) filtering problem in discrete-time state space. An initial result on the strictly passive FIR filter was presented by Ahn in 2012, but was restricted to state-space models with a nonsingular system matrix, which limits the scope of application. In this brief, we propose a new design condition for the strictly passive FIR filter... View full abstract»

• ### A New Unbiased FIR Filter With Improved Robustness Based on Frobenius Norm With Exponential Weight

Publication Year: 2018, Page(s):521 - 525
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This brief proposes a new unbiased finite impulse response (FIR) filter with improved robustness for state-space models in continuous time. The FIR filter proposed in this brief is called the unbiased FIR filter based on the Frobenius norm and exponential weight (UFFFNE). A new integral cost function based on the Frobenius norm for the filter gain function with exponential weight is introduced to ... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org