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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 9 • Date Sept. 2013

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Displaying Results 1 - 25 of 32
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2013 , Page(s): C2
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  • A 0.008 {\hbox {mm}}^{2} 500 /spl mu/W 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation

    Publication Year: 2013 , Page(s): 2241 - 2248
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1803 KB) |  | HTML iconHTML  

    This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 °C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5°C over a temperature range of 0°C ~ 110°C. The entire block occupies 0.008 mm2 in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s. View full abstract»

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  • Information-Theoretic Approach to A/D Conversion

    Publication Year: 2013 , Page(s): 2249 - 2262
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1876 KB) |  | HTML iconHTML  

    We propose a new information theoretic approach to understanding analog-to-digital (A/D) conversion principles. An A/D converter is characterized as a communication system that transmits information from an analog source to the digital domain for processing, storage, transmission, and analysis. Accordingly, an A/D conversion system consists of an analog source of information, a means to sample and encode the analog signal for transmission through the comparator, and a means to decode the digital output from the comparator and provide a digital representation of the analog signal. The comparator acts as a channel since it “injects” uncertainty in the form of quantization noise. We provide an upper bound (conversion capacity) on the amount of information that can be transmitted from the analog to digital domain for a specific A/D converter and we describe a necessary and sufficient condition that, if satisfied, allows an A/D converter to achieve capacity. The conversion capacity defines a fundamental upper limit on the performance of an A/D converter in terms of resolution-bandwidth product for a given technology. It is shown how the conversion capacity may be utilized to yield performance limitations in terms of mean square error and SNR. The capacity is, thus, a useful metric for the comparison of ADC designs and may also provide hints to improving existing and conceiving new A/D conversion methods. View full abstract»

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  • Rapid Wireless Capacitor Charging Using a Multi-Tapped Inductively-Coupled Secondary Coil

    Publication Year: 2013 , Page(s): 2263 - 2272
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1634 KB) |  | HTML iconHTML  

    This paper presents an inductive coupling system designed to wirelessly charge ultra-capacitors used as energy storage elements. Although ultra-capacitors offer the native ability to rapidly charge, it is shown that standard inductive coupling circuits only deliver maximal power for a specific load impedance which depends on coil geometries and separation distances. Since a charging ultra-capacitor can be modeled as an increasing instantaneous impedance, maximum power is thus delivered to the ultra-capacitor at only a single point in the charging interval, resulting in a longer than optimal charging time. Analysis of inductive coupling theory reveals that the optimal load impedance can be modified by adjusting the secondary coil inductance and resonant tuning capacitance. A three-tap secondary coil is proposed to dynamically modify the optimal load impedance throughout the capacitor charging interval. Measurement results show that the proposed architecture can expand its operational range by up to 2.5 × and charge a 2.5 F ultra-capacitor to 5 V upwards of 3.7 × faster than a conventional architecture. View full abstract»

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  • Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications

    Publication Year: 2013 , Page(s): 2273 - 2284
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2614 KB) |  | HTML iconHTML  

    In applications where signal frequencies are high, but information bandwidths are low, analog-to-information converters (AICs) have been proposed as a potential solution to overcome the resolution and performance limitations of high-speed analog-to-digital converters (ADCs). However, the hardware implementation of such systems has yet to be evaluated. This paper aims to fill this gap, by evaluating the impact of circuit impairments on performance limitations and energy cost of AICs. We point out that although the AIC architecture facilitates slower ADCs, the signal encoding, typically realized with a mixer-like circuit, still occurs at the Nyquist frequency of the input to avoid aliasing. We illustrate that the jitter and aperture of this mixing stage limit the achievable AIC resolution. In order to do so, we designed an end-to-end system evaluation framework for examining these limitations, as well as the relative energy-efficiency of AICs versus high-speed ADCs across the resolution, receiver gain and signal sparsity. The evaluation shows that the currently proposed AICs have no performance benefits over high-speed ADCs. However, AICs enable 2-10X in energy savings in low to moderate resolution (ENOB), low gain applications. View full abstract»

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  • A 4-Bit, 1.6 GS/s Low Power Flash ADC, Based on Offset Calibration and Segmentation

    Publication Year: 2013 , Page(s): 2285 - 2297
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2308 KB) |  | HTML iconHTML  

    A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after calibration. The converter offers 3.8 effective number of bits (ENOB) at 1.6 GS/s sampling rate with a low frequency input signal and more than 1.8 GHz effective resolution bandwidth (ERBW) at this sampling rate. The converter consumes mere 15.5 mW from a 1.8 V supply, yielding an FoM of 695 fJ/conversion.step and occupies 0.3 mm2 in a 0.18 μm standard CMOS process. View full abstract»

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  • Integrated Circuit Modeling of Biocellular Post-Transcription Gene Mechanisms Regulated by MicroRNA and Proteasome

    Publication Year: 2013 , Page(s): 2298 - 2310
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2558 KB) |  | HTML iconHTML  

    Regulation of gene expression stages within a cellular creature deals with all the complexities and functionalities of the organism. These genetic information processing activities inside the cell can imitate the specific operations carried out by different combinations of semiconductor devices. Appropriate gene regulation is the basis of correct system biological functionality within all living organisms. Any biochemical aberrations (mutations) in a cell cycle which are not diminished genetically can result in progressive cellular dysfunction. Controlling mutations can be approached by realizing a “silicon mimetic” electronic circuit emulating the gene expression stages. This paper presents an integrated circuit model mimicking the post-transcriptional stages in gene expression regulated by microRNAs and Proteasome. The mRNA degradation by microRNA is modeled using emitter degeneration, while the protein degradation is modeled by a mixed-signal CMOS circuit. The effect of enzymes in the degradation reaction is also explored using a “chemo-inductor.” Probabilistic analysis using Monte Carlo simulations indicates that the proposed staged gene circuit model is also robust in an environment of stochastic biochemical reactions. The model is found to be in close agreement with experimentally reported data. View full abstract»

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  • Compressive Self-Powering of Piezo-Floating-Gate Mechanical Impact Detectors

    Publication Year: 2013 , Page(s): 2311 - 2320
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1887 KB) |  | HTML iconHTML  

    This paper describes a novel compressive self-powering technique that significantly extends the powering and sensing range of our previously reported piezo-floating-gate (PFG) sensors for applications in mechanical impact monitoring. At the core of the proposed technique is a nonlinear impedance circuit that dynamically loads the output of a piezoelectric transducer in a manner such that the sensor can be self-powered at low-levels of mechanical strain and yet is able to sense and detect large variations in strain-levels. The compressive approach requires precise programming of event detection thresholds and requires precise nonvolatile event counting, both of which are achieved using variants of a linear floating-gate injector circuit. Measured results obtained from prototypes fabricated in a 0.5- μm standard CMOS process validate the proposed compressive powering and the proposed programming technique. View full abstract»

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  • A /spl Sigma/ /spl Delta/-FIR-DAC for Multi-Bit /spl Sigma/ /spl Delta/ Modulators

    Publication Year: 2013 , Page(s): 2321 - 2332
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2953 KB) |  | HTML iconHTML  

    In this paper, a new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators (ΣΔMs). This -finite-impulse-response-DAC (ΣΔ-FIR-DAC) digitally converts the multi-bit output of the quantizer to a 1.5-bit signal at a higher rate and then injects it to the modulator loop filter by using a 1.5-bit DAC. An FIR filter is merged into 1.5-bit DAC to improve the clock jitter insensitivity. Furthermore, a new implementation of ΣΔ-FIR-DAC is presented to reduce the output rate of ΣΔ-FIR-DAC down to the original rate of the modulator. This reduced rate ΣΔ-FIR-DAC (RR-ΣΔ-FIR-DAC) can be used in both continuous-time and discrete-time ΣΔMs. Theoretical analysis supported by simulation results are provided to evaluate the performance, clock jitter immunity and robustness against DAC elements mismatch in the proposed modulators. View full abstract»

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  • Low-Voltage Low-Power CMOS Rail-to-Rail Voltage-to-Current Converters

    Publication Year: 2013 , Page(s): 2333 - 2342
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2141 KB) |  | HTML iconHTML  

    This paper presents three compact CMOS voltage-to-current converters based on OTA/common-source configurations, which attain rail-to-rail input-output operation. The three converters present a high impedance input node while provide a highly linear V-I relationship over a ( -40, +120°C) temperature range with a maximum transconductance temperature coefficient of 175 ppm/°C. Measurement results for 1.2-V 0.18- μm CMOS implementations confirm rail-to-rail operation with bandwidths of up to 14.5 MHz and THD of up to -50 dB for 1 Vpp at 100 kHz, active areas below 0.0145 μm2 and power consumption below 85 μW, which make these basic building blocks suitable for portable applications. View full abstract»

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  • Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs

    Publication Year: 2013 , Page(s): 2343 - 2351
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1822 KB) |  | HTML iconHTML  

    Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able to redo the repair and obtain a known good stack (KGS), let alone unused spares be reused. We propose an off-chip repair scheme to deal with the inaccessibility from outside of the memory die. Using a through silicon via (TSV) to access the redundancy control circuit (RCC), we reactivate the unused spares by overwriting their states as if the corresponding fuses are blown. Even when the row or column, which has already been repaired, is damaged again, we are able to replace it with a new spare. Our simulation using a 65 nm process technology shows that the maximum timing penalty of the off-chip repair is only 93ps, compared to the on-chip method. The area overhead is estimated to be 490 μm2 per fuse set by using a 5 μm diameter TSV process. Most importantly, the yield improvement of a two-die stacked memory can be over 50% with yield excursion reduced to 8%. View full abstract»

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  • Output Filter Aware Optimization of the Noise Shaping Properties of ΔΣ Modulators Via Semi-Definite Programming

    Publication Year: 2013 , Page(s): 2352 - 2365
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2172 KB) |  | HTML iconHTML  

    The Noise Transfer Function (NTF) of ΔΣ modulators is typically designed after the features of the input signal. We suggest that in many applications, and notably those involving D/D and D/A conversion or actuation, the NTF should instead be shaped after the properties of the output/reconstruction filter. To this aim, we propose a framework for optimal design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite programming. Some examples illustrate how in practical cases the proposed strategy can outperform more standard approaches. View full abstract»

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  • A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli

    Publication Year: 2013 , Page(s): 2366 - 2374
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1606 KB) |  | HTML iconHTML  

    Recent analyses demonstrate that operations in some bases of Residue Number System (RNS) exhibit higher resiliency to process variations than in normal binary number system. Under this premise, arbitrary moduli offer greater flexibility in forming high cardinality balanced RNS with variation-insensitive small residue operations for a given dynamic range. Limited in number theoretic property, converting an integer into residue for an arbitrary modulus is as difficult as complex arithmetic operation, particularly for very large wordlength ratio of integer to modulus. This paper presents a new design of efficient residue generators and the design approach is demonstrated with large input wordlength of 64 bits for arbitrary moduli of up to 6 bits. The proposed design eliminates the bottleneck carry propagation additions and modular adder tree of existing designs, and circumvents the undesirably high architectural disparity for different moduli of inconsistent cyclic periodicity. Our experimental results on moduli of different periodicities show that the proposed design is on average 27.7% faster and 28.7% smaller than the state-of-the-art residue generator. Our power simulation results also show that the proposed residue generator has on average reduced the total power and the leakage power of the latter by 44.5% and 24.7%, respectively. View full abstract»

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  • Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error

    Publication Year: 2013 , Page(s): 2375 - 2388
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4519 KB) |  | HTML iconHTML  

    Fixed-width multipliers have two n-bits operands and produce an approximate n-bits results for their product. These multipliers discard part of the partial products matrix, to reduce hardware cost, and employ extra correction functions to reduce approximation error. While previous papers mainly focus on average error metrics (like mean-square error), we present an in-depth analysis of the maximum absolute error (MAE) of these circuits. The MAE is the main parameter to be considered in important applications, like function evaluation. We describe an efficient numerical method to compute the MAE in fixed-width multipliers and fixed-width multiplier-accumulator (MAC) circuits. Further we present a technique to compute a compensation function, that can be efficiently implemented in hardware, aimed to minimize the MAE. The novel fixed-width multiplier topologies proposed in the paper exhibit a MAE that is better than previously proposed solutions and that is close to the theoretical lower bound. As a practical application we employ the developed MAC with minimum MAE for the hardware computation of elementary functions, using piecewise linear approximation. Implementation results in a 65 nm technology and comparison with previously proposed architectures show that the topologies proposed in this paper allow reducing the MAE without worsening the electrical performances. View full abstract»

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  • A Common Subexpression Elimination Tree Algorithm

    Publication Year: 2013 , Page(s): 2389 - 2400
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1947 KB) |  | HTML iconHTML  

    A common subexpression elimination algorithm is proposed to minimize the complexity of the multiple constant multiplication operation. The coefficients (constants) of the multiple constant multiplication are represented using the binary signed digit number system. The binary signed digit representations of each coefficient are enumerated using the representation tree. The algorithm traverses the tree to calculate the possible subexpressions at each node. Each subexpression is used to find a possible decomposition for the coefficient to be encoded. A complexity formula is proposed to compare the decompositions. The algorithm is designed to prune the tree when it finds a decomposition with minimum complexity. This reduces the search space while minimizing the hardware complexity. Results show that the algorithm has better performance than other published algorithms including linear programming optimization methods. The algorithm outperforms the subexpression sharing method in that uses only the canonical signed-digit representations. View full abstract»

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  • Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops

    Publication Year: 2013 , Page(s): 2401 - 2411
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2124 KB) |  | HTML iconHTML  

    For synchronous designs, a large portion of the total power consumption of the integrated circuit (IC) is due to the storage elements and the clock distribution. Energy efficiency from the clock elements plays a critical role in low-power circuit design. One technique for efficiency is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Clock gating is another well-accepted technique to reduce the dynamic power of idle modules or idle cycles. However, incorporating clock gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling (i.e., a change in output between clock edges) that was not addressed in previous research. This asynchronous data sampling is explored in detail in this paper by analyzing the mechanisms of several different clock-gated DETFFs. Three special clock-gating strategies are evaluated to mitigate this issue in DETFFs. Each of these three solutions has limitations, and the respective tradeoffs are discussed. View full abstract»

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  • Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead

    Publication Year: 2013 , Page(s): 2412 - 2421
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1224 KB) |  | HTML iconHTML  

    With the aggressive technology scaling and use of multi-bit per cell storage, NAND flash memory is subject to continuous degradation of raw storage reliability and demands more and more powerful error correction codes (ECC). This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as LDPC codes become very natural alternative options. However, these powerful coding solutions demand soft-decision memory sensing, which results in longer on-chip memory sensing latency and memory-to-controller data transfer latency. Leveraging well-established lossless data compression theories, this paper presents several simple design techniques that can reduce such latency penalty caused by soft-decision ECCs. Their effectiveness have been well demonstrated through extensive simulations, and the results suggest that the latency can be reduced by up to 85.3%. View full abstract»

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  • FFT Architectures for Real-Valued Signals Based on Radix- 2^{3} and Radix- 2^{4} Algorithms

    Publication Year: 2013 , Page(s): 2422 - 2430
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1522 KB) |  | HTML iconHTML  

    This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix- 2n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix- 23 and radix- 24 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix- 23 and radix- 24 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix- 24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements. View full abstract»

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  • Exponential Synchronization of Delayed Neural Networks With Discontinuous Activations

    Publication Year: 2013 , Page(s): 2431 - 2439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2755 KB) |  | HTML iconHTML  

    This paper investigates drive-response synchronization of a class of neural networks with time-varying delays and discontinuous activations. Discontinuous state feedback controller and adaptive controller are designed such that the considered model can realize exponential complete synchronization. Moreover, the convergence rate is explicitly estimated when state feedback control is utilized. The obtained results are also applicable to neural networks with continuous activations since they are a special case of neural networks with discontinuous activations. Results of this paper improve corresponding ones which only quasi-synchronization can be achieved for neural networks with discontinuous activations. Finally, numerical simulations are given to verify the effectiveness of the theoretical results. View full abstract»

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  • Exponential H_{\infty } Filtering for Singular Markovian Jump Systems With Mixed Mode-Dependent Time-Varying Delay

    Publication Year: 2013 , Page(s): 2440 - 2452
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4613 KB) |  | HTML iconHTML  

    This paper is concerned with the exponential H filter design for a class of continuous-time singular Markovian jump systems with mixed mode-dependent time-varying delay. By constructing a new Lyapunov-Krasovskii functional and utilizing some advanced techniques, a less conservative delay-dependent bounded real lemma (BRL) is obtained in terms of linear matrix inequalities (LMIs), which guarantees the considered system is exponentially admissible with H performance. Based on the BRL, the H filtering problem is solved and an explicit expression of the desired filter can be given. Two numerical examples are presented to illustrate the effectiveness and the potential of the proposed techniques. View full abstract»

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  • Optimal Fraction-Free Routh Tests for Complex and Real Integer Polynomials

    Publication Year: 2013 , Page(s): 2453 - 2464
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3407 KB) |  | HTML iconHTML  

    The Routh test is the simplest and most efficient algorithm to determine whether all the zeros of a polynomial have negative real parts. However, the test involves divisions that may decrease its numerical accuracy and are a drawback in its use for various generalized applications. The paper presents fraction-free forms for this classical test that enhance it with the property that the testing of a polynomial with Gaussian or real integer coefficients can be completed over the respective ring of integers. Two types of algorithms are considered one, named the G-sequence, which is most efficient (as an integer algorithm) for Gaussian integers, and another, named the R-sequence, which is most efficient for real integers. The G-sequence can be used also for the real case, but the R-sequence is by far more efficient for real integer polynomials. The count of zeros with positive real parts for normal polynomials is also presented for each algorithm. View full abstract»

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  • Realizations of a Special Class of Admittances With Strictly Lower Complexity Than Canonical Forms

    Publication Year: 2013 , Page(s): 2465 - 2473
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1949 KB) |  | HTML iconHTML  

    This paper investigates the simplified realization problem of a special class of positive-real admittances similar to biquadratic functions but with an extra pole at the origin, which is widely used in the analysis of suspension systems. The results in this paper are motivated by passive mechanical control with the inerter. The concept of strictly lower complexity is first defined, whose indices in this paper are the total number of elements, the number of resistors (dampers), and the number of capacitors (inerters). We then derive a necessary and sufficient condition for this class of admittance to be realized by the networks that are of strictly lower complexity than the canonical realization by the Foster Preamble method. To solve this problem, it is shown that it suffices to consider the following: 1) networks with at most four elements, 2) irreducible five-element resistor-inductor (RL) networks, and 3) irreducible five-element resisitor-inductor-capacitor (RLC) networks. Other cases are shown to be impossible. By finding their corresponding network configurations through a series of constraints and deriving the corresponding realizability conditions, the final condition can be obtained. Finally, the U-V plane and numerical examples are provided to illustrate the theoretical results. View full abstract»

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  • Theoretic Bounds to Information Transmission Through Electrical Circuits

    Publication Year: 2013 , Page(s): 2474 - 2487
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2353 KB) |  | HTML iconHTML  

    The paper investigates the fundamental limits of communication over electrical multiple-input-multiple-output (MIMO) networks in which information transmission is associated to energy exchanges. We first develop the computation of the Shannon capacity of a MIMO, wideband, frequency-dependent, time-invariant channel. This gives us the fundamental equations linking the achievable bit-rate, the needed power and its distribution over the necessary bandwidth. Such equations are then specialized to a general cascade of electrical stages and further detailed to tackle the case of a specific lumped elements circuit. With reference to such a circuit the effectiveness of the method is demonstrated by addressing simple cases which highlight the role of different kinds of coupling between electrical paths. Finally, the case of transmission over intra-chip buses realized with a real-world silicon technology is addressed, for which the effect of massive parallelism is discussed. View full abstract»

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  • A Crystal-Less Self-Synchronized Bit-Level Duty-Cycled IR-UWB Transceiver System

    Publication Year: 2013 , Page(s): 2488 - 2501
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2772 KB) |  | HTML iconHTML  

    A self-synchronized dual-band OOK IR-UWB transceiver system for short-range, low-data rate sensor networks is demonstrated. The transceiver system utilizes asynchronous non-coherent energy detection coupled with a novel pulse-coupled injection-locking scheme to synchronize transceivers throughout the network at nanosecond-scale precision. The pulse-coupled synchronization scheme compensates for intrinsic frequency variation so that all timing in the system can be derived from an integrated relaxation oscillator operating at a nominal frequency of 150 KHz. A low-jitter PLL and simple combinational logic is used for timing generation and control. The system is duty cycled between the expected arrival times of the sync and data pulses, allowing a demonstrated average RF duty cycle of less than 1% while being able to maintain synchronization for nearly 1 million cycles. Total measured system power consumption is 119 μW while actively communicating with 1200 bit packets. The transceiver was designed in a 90 nm IBM CMOS process and occupies 1.7 mm2 of active area. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras