# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 38

Publication Year: 2019, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2019, Page(s): C2
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• ### Improving Receiver Close-In Blocker Tolerance by Baseband $G_m-C$ Notch Filtering

Publication Year: 2019, Page(s):885 - 896
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This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offs... View full abstract»

• ### An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation

Publication Year: 2019, Page(s):897 - 908
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An on-chip built-in linearity estimation methodology for a hybrid baseband chain is proposed. The proposed hybrid baseband chain consists of a continuous-time low-pass filter and a discrete-time (DT) finite impulse response filter with a compacted two-stage 3-tap harmonic cancellation (HC). This HC-32 architecture achieves notching at specific programmable frequency points. To estimate ... View full abstract»

• ### A 1-MHz-Bandwidth Gm-C-Based Quadrature Bandpass Sigma-Delta Modulator Achieving −153.7-dBFS/Hz NSD With Background Calibration

Publication Year: 2019, Page(s):909 - 919
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This paper presents a fifth-order continuous-time Gm-C-based quadrature bandpass sigma-delta ( $\Delta \Sigma$ ) modulator for Internet-of-Things applications. In the presented $\Delta \Sigma$ modulator, a reconfigurable full-scale input amplitude assists... View full abstract»

• ### Clock Jitter Analysis of Continuous-Time $\Sigma\Delta$ Modulators Based on a Relative Time-Base Projection

Publication Year: 2019, Page(s):920 - 929
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This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma–delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the in... View full abstract»

• ### Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity

Publication Year: 2019, Page(s):930 - 940
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In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype ima... View full abstract»

• ### Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

Publication Year: 2019, Page(s):941 - 954
Cited by:  Papers (1)
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This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved stor... View full abstract»

• ### Physically Unclonable Functions Using Foundry SRAM Cells

Publication Year: 2019, Page(s):955 - 966
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This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variabili... View full abstract»

• ### Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

Publication Year: 2019, Page(s):967 - 977
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In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times$ and $3.4\times$ the minimum critical charge of the conventional 6T, respectively. Compared with m... View full abstract»

• ### Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Publication Year: 2019, Page(s):978 - 988
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The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and View full abstract»

• ### Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation

Publication Year: 2019, Page(s):989 - 1002
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Pseudorandom bit generator (PRBG) is an essential component for securing data during transmission and storage in various cryptography applications. Among popular existing PRBG methods such as linear feedback shift register (LFSR), linear congruential generator (LCG), coupled LCG (CLCG), and dual-coupled LCG (dual-CLCG), the latter proves to be more secure. This method relies on the inequality comp... View full abstract»

• ### High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication

Publication Year: 2019, Page(s):1003 - 1016
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In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications ... View full abstract»

• ### Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays

Publication Year: 2019, Page(s):1017 - 1030
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We consider a digital encoding/processing system in which both the analog-to-digital converter and the digital signal processor are implemented by repeating a single fundamental design unit: the digital delay. Timing becomes an integral part of the resulting signal representation and processing, thereby promising to improve with technology scaling. System properties are studied and design consider... View full abstract»

• ### An Adaptive Cascaded ILA- and DLA-Based Digital Predistorter for Linearizing an RF Power Amplifier

Publication Year: 2019, Page(s):1031 - 1041
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This paper presents a novel adaptive digital predistortion (DPD) technique based on a cascade of an adaptive indirect learning architecture (ILA) and a static direct learning architecture (DLA) using a linear interpolation look-up-table (LILUT). The static LILUT-DLA-based DPD is designed to identify the inverse of a radio-frequency power amplifier (PA) model. The cascaded system of the DLA-based p... View full abstract»

• ### Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data

Publication Year: 2019, Page(s):1042 - 1050
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Efficient computation of real-valued fast Fourier transform (RFFT) has received significant attention in recent years due to its several applications in conventional digital signal processing and other emerging areas. In-place RFFT architectures are gaining popularity due to their lower hardware complexity compared with pipeline architectures. But the scaling of in-place RFFT architecture for high... View full abstract»

• ### Mean-Square Analysis of Multi-Sampled Multiband-Structured Subband Filtering Algorithm

Publication Year: 2019, Page(s):1051 - 1062
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Although the multiband-structured subband adaptive filter (MSAF) and its convergence analysis have been widely studied, the existing analyses are carried out only in the decimated time domain. In this paper, we present a new theoretical mean-square analysis of the multi-sampled MSAF (MS-MSAF) algorithm in the original time domain, whereas the MS-MSAF algorithm extends the original sub-sampled numb... View full abstract»

• ### Statistics-Based Approach for Blind Post-Compensation of Modulator’s Imperfections and Power Amplifier Nonlinearity

Publication Year: 2019, Page(s):1063 - 1075
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Power amplifier (PA) nonlinearity and in-phase and quadrature-phase (I/Q) imbalance are major concerns for wireless transmitters. In this paper, we present a new closed-form expression for the probability density function (PDF) of I and Q components in the presence of transmitter’s impairments and propose a blind post-compensation approach for the mitigation of these impairments. These impairments... View full abstract»

• ### Event-Triggered Finite-Time Robust Filtering for a Class of State-Dependent Uncertain Systems With Network Transmission Delay

Publication Year: 2019, Page(s):1076 - 1089
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In this paper, the event-triggered robust filtering problem is investigated for a class of network-based state-dependent uncertain systems in the sense of finite-time boundedness, considering network transmission delay. By resorting to a generalized performance index, the $H_\infty$ and View full abstract»

• ### Network Science Meets Circuit Theory: Resistance Distance, Kirchhoff Index, and Foster’s Theorems With Generalizations and Unification

Publication Year: 2019, Page(s):1090 - 1103
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The emerging area of network science and engineering is concerned with the study of structural characteristics of networks, their impact on the dynamical behavior of systems as revealed through their topological properties, random evolution of networks, information spreading along a network, and so on. This area spans a wide range of applications in different disciplines. A topic of great interest... View full abstract»

• ### Proper Initial Solution to Start Periodic Steady-State-Based Methods

Publication Year: 2019, Page(s):1104 - 1115
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We present a numerical technique that automatically identifies a suitable initial solution to start periodic steady-state methods for simulating non-autonomous circuits at transistor-level. The method avoids the guessing of the initial solution, which may result in divergence of the steady-state method used. For high-Q oscillating circuits, acceleration methods are used to compute the periodic sol... View full abstract»

• ### ${{H}_{\infty}}$ Model Reduction for Interval Frequency Negative Imaginary Systems

Publication Year: 2019, Page(s):1116 - 1129
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This paper studies an $H_{\infty }$ model reduction problem for interval frequency negative imaginary (IFNI) systems. For a given IFNI system, our goal is to find a reduced-order IFNI system satisfying a pre-specified $H_{\infty }$ approximation error bo... View full abstract»

• ### Network-Based Quantized Control for Fuzzy Singularly Perturbed Semi-Markov Jump Systems and its Application

Publication Year: 2019, Page(s):1130 - 1140
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This paper deals with the quantized control problem for nonlinear semi-Markov jump systems subject to singular perturbation under a network-based framework. The nonlinearity of the system is well solved by applying Takagi–Sugeno (T-S) fuzzy theory. The semi-Markov jump process with the memory matrix of transition probability is introduced, for which the obtained results are more reasonable and les... View full abstract»

• ### Synchronization of Multi-Layer Networks: From Node-to-Node Synchronization to Complete Synchronization

Publication Year: 2019, Page(s):1141 - 1152
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Multi-layer networks, which incorporate multiple subsystems and different kinds of interactions, are recently believed to have a stronger ability in modelling various real-world systems than traditional single-layer complex networks. Motivated by this observation, we try to show how to achieve node-to-node synchronization and complete synchronization in multi-layer networks under directed switchin... View full abstract»

• ### A Hilbert Transform Equalizer Enabling 80 MHz RF Self-Interference Cancellation for Full-Duplex Receivers

Publication Year: 2019, Page(s):1153 - 1165
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A passive, time-domain equalizer is presented that achieves a broadband self-interference cancellation (SIC) over 80 MHz of RF bandwidth for simultaneous full-duplex radios. A baseband Hilbert transform technique reduces the number of equalizer taps needed for SIC, and with frequency translations, results in an equivalent RF-domain equalization. A proof-of-concept prototype in 0.13- View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK