# IEEE Transactions on Circuits and Systems I: Regular Papers

## Issue 11 • Nov. 2018

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## Filter Results

Displaying Results 1 - 25 of 44
• ### Table of contents

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
| PDF (112 KB)
• ### Guest Editorial Special Issue on the 2018 International Symposium on Integrated Circuits and Systems

Publication Year: 2018, Page(s): 3605
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• ### A 0.19 mm210 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

Publication Year: 2018, Page(s):3606 - 3616
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This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a f... View full abstract»

• ### A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-$\mu$m CMOS

Publication Year: 2018, Page(s):3617 - 3627
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This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta ($\Delta$) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but a... View full abstract»

• ### A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation

Publication Year: 2018, Page(s):3628 - 3638
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A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of$3.2\,\,V_{\mathrm {pp-d}}$($\pm 1.33~V_{\text {REF}}$ View full abstract»

• ### A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC

Publication Year: 2018, Page(s):3639 - 3650
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This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lowe... View full abstract»

• ### Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion

Publication Year: 2018, Page(s):3651 - 3661
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This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta–sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist$M$ View full abstract»

• ### Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators

Publication Year: 2018, Page(s):3662 - 3674
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Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ($\Delta \Sigma$Ms) are discussed. These tech... View full abstract»

• ### A 0.9-V 100-$\mu$W Feedforward Adder-Less Inverter-Based MASH$\Delta\Sigma$Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth

Publication Year: 2018, Page(s):3675 - 3687
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A 0.9-V$\Delta \Sigma$modulator integrated into a 0.18-$\mu \text{m}$CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (multistage noise shaping) architecture based on anadder-lessfe... View full abstract»

• ### A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver

Publication Year: 2018, Page(s):3688 - 3697
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This paper presents a 12-bit multi-channel resistor–resistor-string digital-to-analog converter (RRDAC) using a shared R-string scheme for an area efficient display source driver. The proposed scheme relaxes the required equivalent resistance value of R-string of each channel by sharing a channel R-string that is simultaneously connected to the same tap of a global R-string. Thus, the overall DAC ... View full abstract»

• ### A 4-Channel 12-Bit High-Voltage Radiation-Hardened Digital-to-Analog Converter for Low Orbit Satellite Applications

Publication Year: 2018, Page(s):3698 - 3706
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This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5-$\mu \text{m}$Bi-CMOS technology to achieve the functionality across a wide-temperature range from −55 °C to 125 °C. I... View full abstract»

• ### Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC

Publication Year: 2018, Page(s):3707 - 3719
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This paper reports a calibration scheme that can be used to correct the inter-stage gain error in two-stage analog-to-digital converters (ADCs). We measure the static nonlinearity at the raw ADC outputs and compensate it through a feedback path to adjust the gain in the analog domain, which avoids the dynamic range loss in the conventional pure digital calibrations. The proposed scheme detects the... View full abstract»

• ### A 25-Gb/s 270-mW Time-to-Digital Converter-Based$8{\times}$Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

Publication Year: 2018, Page(s):3720 - 3733
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This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential dela... View full abstract»

• ### An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order$\Delta\Sigma$Loop

Publication Year: 2018, Page(s):3734 - 3744
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To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order$\Delta \Sigma$time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurement... View full abstract»

• ### A Mixed-Signal Circuit Technique for Cancellation of Interferers Modulated by LO Phase-Noise in 4G/5G CA Transceivers

Publication Year: 2018, Page(s):3745 - 3755
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In RF transceivers operating in carrier-aggregation, spurs are generated on the transceiver chip which may down-convert any blocker signal located at the spur frequency into the receiver baseband. The blocker signal could either be the transceiver’s own transmit signal when operating in frequency-division duplex, or a WiFi-related signal received by the antenna. This so-called modulated spur inter... View full abstract»

• ### An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

Publication Year: 2018, Page(s):3756 - 3768
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We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains ... View full abstract»

• ### Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits

Publication Year: 2018, Page(s):3769 - 3779
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In this paper, a technique for slew-rate (SR) boosting suitable for switched-capacitor circuits is proposed. The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals. The proposed architecture employs simple circuitry to detect the need for a large output current by employing a highly sensitive pre-amplif... View full abstract»

• ### Class-J SiGe$X$-Band Power Amplifier Using a Ladder Filter-Based AM–PM Distortion Reduction Technique

Publication Year: 2018, Page(s):3780 - 3789
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In this paper, a class-J power amplifier for operation in the X-band realized in SiGe bipolar technology is presented. The proposed design combines the high efficiency of class-J operation with solutions to mitigate AM-PM distortion down to a level compatible with high spectral efficiency modulation schemes like 64-QAM. The design of a transformer-based output matching network and the trade-off be... View full abstract»

• ### A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems

Publication Year: 2018, Page(s):3790 - 3799
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In this paper, we propose an ultra-low power compact 3-transistor voltage reference capable of operating at ultra-low supply voltages. The proposed circuit is based on the self-cascode MOSFET (SCM), which provides a reference voltage proportional to the threshold voltage ($V_{T}$) difference of the two NMOS transistors that com... View full abstract»

• ### A Fully Integrated Analog Front End for Biopotential Signal Sensing

Publication Year: 2018, Page(s):3800 - 3809
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A low-power fully-integrated analog front end for biopotential sensors is proposed. The signal conditioning circuitry features an integrating sampler and a digital-assisted electrode offset-cancellation loop. The chip is fabricated in a standard 0.18-$\mu \text{m}$CMOS process. The supply voltage is 1.2 V and the quiescent curr... View full abstract»

• ### A High Frame Rate Wearable EIT System Using Active Electrode ASICs for Lung Respiration and Heart Rate Monitoring

Publication Year: 2018, Page(s):3810 - 3820
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A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all ... View full abstract»

• ### A CMOS Temperature Sensor With Versatile Readout Scheme and High Accuracy for Multi-Sensor Systems

Publication Year: 2018, Page(s):3821 - 3829
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In this paper, a smart CMOS temperature sensor with a versatile readout scheme is presented. A digital-assisted readout solution is proposed to improve the compatibility of the circuit and maintain the performance of a traditional smart temperature sensor. In addition, the potential multi-operating points of the analog front-end are analyzed, and a compact start-up circuit is designed to make the ... View full abstract»

• ### An Analog CMOS Silicon Photomultiplier Using Perimeter-Gated Single-Photon Avalanche Diodes

Publication Year: 2018, Page(s):3830 - 3841
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Perimeter-gated single-photon avalanche diodes (PGSPADs) have been shown to mitigate premature edge breakdown without unduly increasing the area of the device. PGSPADs are three terminal devices. In this paper, we develop a probability-based SPICE model for the PGSPAD and fully characterize an$18 \times 18$pixel analog PGSPAD-b... View full abstract»

• ### A Low-Power Vision System With Adaptive Background Subtraction and Image Segmentation for Unusual Event Detection

Publication Year: 2018, Page(s):3842 - 3853
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This paper presents a smart ultra-low power vision system targeted to video surveillance applications. The sensor embeds a low-level image processing technique that autonomously detects unusual events occurring in the scene, relying on adaptive background subtraction. The resulting binary image is then directly segmented by an FPGA, which triggers the higher layer of processing, transferring only ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK