# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 41

Publication Year: 2019, Page(s):C1 - C4
| PDF (176 KB)
• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2019, Page(s): C2
| PDF (77 KB)
• ### Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Publication Year: 2019, Page(s):1 - 19
| | PDF (1696 KB) | HTML

Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often limits the performance of such systems. Hence, a deep understanding of how oscillator performance is quantified, simulated, and measured, and how it affects the system performance is essential for designers. Unfortunately, the necessary information is spread thinly across the published literature and textbo... View full abstract»

• ### A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique

Publication Year: 2019, Page(s):20 - 30
| | PDF (2474 KB) | HTML

A performance-boosting frequency-compensation technique, called feed-forward Gm-stage and regular Miller plus indirect compensation (FGRMIC), is presented in this paper. The proposed structure consists of three parts that ensure the stability and significantly improve the performance, such as gain–bandwidth product (GBW), slew rate, and sensitivity. The first part is a feed-forward transconductanc... View full abstract»

• ### A 2.4 GHz CMOS Class-F Power Amplifier With Reconfigurable Load-Impedance Matching

Publication Year: 2019, Page(s):31 - 42
| | PDF (3541 KB) | HTML

A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output... View full abstract»

• ### A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter

Publication Year: 2019, Page(s):43 - 53
| | PDF (3569 KB) | HTML

Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently because of two major limitations—limited lock-range and large reference spurs. This paper introduces a type-I PLL that takes advantage of the inherent benefits of the architecture, while tackling its limitati... View full abstract»

• ### A 1-$\mu$s Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration

Publication Year: 2019, Page(s):54 - 67
| | PDF (5494 KB) | HTML

This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered ... View full abstract»

• ### Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs

Publication Year: 2019, Page(s):68 - 81
| | PDF (4175 KB) | HTML

This paper analyzes the intermodulation between the element transition rate and the output-dependent unit switching distortion, i.e., the switching distortion of one switching unit, in current-steering digital-to-analog converters (DACs). The analysis and experimental results reveal how this intermodulation affects the DAC linearity. Based on this, we also propose a technique, termed random pairwi... View full abstract»

• ### Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC

Publication Year: 2019, Page(s):82 - 93
| | PDF (2376 KB) | HTML

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available t... View full abstract»

• ### An On-Chip Linear, Squaring, Cubic and Exponential Analog Function Generator

Publication Year: 2019, Page(s):94 - 104
| | PDF (3178 KB) | HTML

This paper presents a novel technique based on the current steering technique for the generation of a reconfigurable current that approximates the linear, squaring, cubic, and exponential and their descending analog functions. The proposed implementation can be easily programmed to generate these functions by simply reconfiguring the weighting factors of current sources and offers an extendable in... View full abstract»

• ### A Broadband Multi-Mode Compressive Sensing Current Sensor SoC in 0.16$\mu$m CMOS

Publication Year: 2019, Page(s):105 - 118
| | PDF (2813 KB) | HTML

Broadband current sensors are key components in numerous applications, including power conversion, motor control, and smart-metering. We present a compressive sensing (CS) current sensor system-on-chip (SoC) designed and fabricated in STM 0.16$\mu \text{m}$Bipolar-CMOS-DMOS technology. The SoC is capable of measuring currents w... View full abstract»

• ### Dual-Band Transmission-Line Resistance Compression Network and Its Application to Rectifiers

Publication Year: 2019, Page(s):119 - 132
| | PDF (5050 KB) | HTML

In this paper, a dual-band transmission-line resistance compression network (TLRCN) is introduced and applied to the rectifier design to enhance the power conversion efficiency at low input power levels, leading to wider dynamic power range of the rectifier. It can be used to reduce the sensitivity of the rectifying efficiency to input power variation at two frequencies. The analytical expressions... View full abstract»

• ### On the Design of$n$th-Order Polyphase All-Pass Filters

Publication Year: 2019, Page(s):133 - 146
| | PDF (2889 KB) | HTML

• ### Ultra-Dense Ring-Shaped Racetrack Memory Cache Design

Publication Year: 2019, Page(s):215 - 225
| | PDF (3504 KB) | HTML

Information storage and transfer via current-induced domain wall (DW) motions exhibit significant density-speed-energy advantages, which inspires numerous emerging devices and circuits, such as racetrack memory (RM). However, the bi-directional propagation of DWs in the conventional tape-shaped nanowire will lead to data overflow issue, implicitly deteriorating storage density and operational perf... View full abstract»

• ### Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD

Publication Year: 2019, Page(s):226 - 238
| | PDF (3450 KB) | HTML

Hybrid solid state drive based on ReRAM and NAND flash technologies has shown promising performance and energy efficiency. In this application, ReRAM is mainly used as a non-volatile buffer to hold recently accessed data pages or address mapping information. The previous studies on the ReRAM-based buffer mainly focus on performance and efficiency improvement, while reliability issues are not taken... View full abstract»

Publication Year: 2019, Page(s):239 - 250
| | PDF (4382 KB) | HTML

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on... View full abstract»

• ### HCDN: Hybrid-Mode Clock Distribution Networks

Publication Year: 2019, Page(s):251 - 262
| | PDF (2408 KB) | HTML

We propose a new hybrid clock distribution scheme that uses global current-mode and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking... View full abstract»

• ### Overhead Requirements for Stateful Memristor Logic

Publication Year: 2019, Page(s):263 - 273
| | PDF (3580 KB) | HTML

Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristo... View full abstract»

• ### SensorNet: A Scalable and Low-Power Deep Convolutional Neural Network for Multimodal Data Classification

Publication Year: 2019, Page(s):274 - 287
| | PDF (4034 KB) | HTML

This paper presents SensorNet which is a scalable and low-power embedded deep convolutional neural network (DCNN), designed to classify multimodal time series signals. Time series signals generated by different sensor modalities with different sampling rates are first converted to images (2-D signals), and then DCNN is utilized to automatically learn shared features in the images and perform the c... View full abstract»

• ### FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks

Publication Year: 2019, Page(s):288 - 301
| | PDF (3495 KB) | HTML

Emerging convolutional neural networks (CNNs) tend to be designed with varied per-layer data widths and sparse representations. However, these two features, which bring many redundant computations, have not been exploited simultaneously in existing hardware architectures for CNNs. This paper proposes an energy-quality scalable architecture, namely folded precision-adjustable processor (FPAP), to e... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK