2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

16-18 Dec. 2002

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  • 2002 IEEE International Conference on Field-Programmable Technology (FPT). Proceedings (Cat. No.02EX603)

    Publication Year: 2002
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  • Technology research and development in Hong Kong: hype or reality

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB) | HTML iconHTML

    Looks at the development of innovation and technology funding, infrastructure and achievements in Hong Kong in the past few years, and examine the potential areas where Hong Kong can excel and be a significant contributor to technology development. Comparison will be drawn from Finland, an economy of a size and GDP very similar to that of Hong Kong. View full abstract»

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  • The hot decade of field programmable technologies

    Publication Year: 2002, Page(s):3 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (182 KB) | HTML iconHTML

    A historical review of the chip industry will be provided with the emphasis on the cyclical nature between standardization direction and customization direction. The basic mechanisms of the cycle will be discussed including technology factors and marketing factors. It is concluded that the field programmable technology will play the vital role in the emerging digital consumer market by providing f... View full abstract»

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  • FPGAs as meta-platforms for embedded systems

    Publication Year: 2002, Page(s):7 - 12
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    Platform-based design is one of the key strategies that is promoted for successfully coping with the most complex, system-on-chip designs. Its basic premise is that the levels of design productivity needed to counter the intrinsic complexity of such embedded systems will only be achieved by extensive, planned design re-use. The platform concept originated with ASICs but evolved rapidly to FPGAs. I... View full abstract»

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  • Programmed solutions: the step beyond programmed logic [computer architecture]

    Publication Year: 2002, Page(s):13 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    The task of computer architecture is to match a user application with a base technology. This match is realized by implementing an interpreter of some representation of the application with an efficient realization, measured in cost (area), time (performance) and power. As silicon technology becomes increasingly limited by interconnects, more efficient cellular computers are attractive. Indeed lar... View full abstract»

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  • The next big leap in reconfigurable systems

    Publication Year: 2002, Page(s):17 - 22
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB) | HTML iconHTML

    The age of adaptive computing is upon us, empowering the engineering community with the next big leap in computing; one in which algorithmic elements are mapped directly on to dynamic hardware resources to create the exact hardware needed for a task, clock cycle by clock cycle. The outcome of this powerful concept is a computing platform that combines the best of hardware and software into a power... View full abstract»

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  • Real-time packet editing using reconfigurable hardware for active networking

    Publication Year: 2002, Page(s):26 - 33
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB) | HTML iconHTML

    An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, actio... View full abstract»

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  • Implementation of an FPGA based accelerator for virtual private networks

    Publication Year: 2002, Page(s):34 - 41
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (409 KB) | HTML iconHTML

    Virtual Private Networks (VPN) are becoming increasingly popular network architectures for corporate networks. As VPNs are built on the Internet infrastructure, the data exchange among different local area networks will be passed through the Internet and thus can be easily eavesdropped, masqueraded, etc. Therefore, certain security measures must be used to deal with these privacy issues. The Inter... View full abstract»

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  • Compiling run-time parametrisable designs

    Publication Year: 2002, Page(s):44 - 51
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB) | HTML iconHTML

    This paper explores representations and compilation of run-time parametrisable FPGA designs. We develop methods to produce designs with many run-time parameters, which would otherwise require an impractical number of bitstreams to be generated at compile time. Run-time parametrisation facilitates specialisation, which can be used to remove logic to produce a smaller and faster design. Our approach... View full abstract»

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  • Adaptive FIR filter architectures for run-time reconfigurable FPGAs

    Publication Year: 2002, Page(s):52 - 59
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    This paper presents a technique for realizing adaptive FIR filters that use constant-coefficient multipliers on a run-time reconfigurable FPGA. Three different adaptive FIR filter architectures for run-time reconfigurable FPGAs are presented. It is shown that run-time reconfigurable logic can be used to efficiently implement adaptive constant-coefficient FIR filters. With reasonable configuration ... View full abstract»

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  • A methodology for design of run-time reconfigurable systems

    Publication Year: 2002, Page(s):60 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB) | HTML iconHTML

    Field-programmable logic (FPL) is rapidly becoming established in markets requiring high-performance, low lead time and the ability to perform soft-upgrades on site. However few current FPL systems utilise run-time reconfiguration (RTR) and those that do rely on infrequent and coarse-grained reconfiguration. This is partly due to poor support from current FPGAs; few devices allow random access to ... View full abstract»

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  • Resource-aware run-time elaboration of behavioural FPGA specifications

    Publication Year: 2002, Page(s):68 - 75
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    The Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned,... View full abstract»

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  • Multiplier-less FIR digital filters using programmable sum-of-power-of-two (SOPOT) coefficients

    Publication Year: 2002, Page(s):78 - 84
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    This paper proposes a new architecture for the implementation of multiplier-less FIR digital filters with programmable sum-of-powers-of-two (SOPOT) or canonical signed digit (CSD) coefficient representations. The multiplier-less FIR filter is implemented as the direct form structure with the filter coefficients represented as SOPOT representation, which can be realized as limited number of shifts ... View full abstract»

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  • FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator

    Publication Year: 2002, Page(s):85 - 92
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    A system level design framework for FPGA-based DSP design is presented. The design flow utilizes System Generator, a system level tool developed by Xilinx, and links it to an "in-house" architectural synthesis tool, IRIS. Whilst System Generator allows FPGA-based Intellectual Property (IP) cores to be incorporated into the design flow, it does not address the timing and latency problems introduced... View full abstract»

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  • Area and time efficient implementations of matrix multiplication on FPGAs

    Publication Year: 2002, Page(s):93 - 100
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (485 KB) | HTML iconHTML

    We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the previous designs and our design are 14.45, 4.93, and 2.35, respe... View full abstract»

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  • A system level implementation of Rijndael on a memory-slot based FPGA card

    Publication Year: 2002, Page(s):102 - 109
    Cited by:  Papers (2)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (497 KB) | HTML iconHTML

    This paper describes system level issues encountered in a high performance implementation of a Rijndael encryption core on a memory-slot based reconfigurable computing platform called Pilchard. The Rijndael algorithm was adopted in 2000 by the US National Institute of Standards and Technology (NIST) as the Advanced Encryption Standard (AES). In the implementation of Rijndael, changing the number o... View full abstract»

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  • FPGA-based cloud detection for real-time onboard remote sensing

    Publication Year: 2002, Page(s):110 - 116
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (417 KB) | HTML iconHTML

    Reconfigurable computing is an enabling technology for real-time image processing onboard remote sensing satellites. This can potentially reduce the delay between image capture, analysis and action, and also reduce onboard storage and downlink capacity requirements. This paper discusses the design and implementation of a real-time cloud detection system intended for use within an onboard remote se... View full abstract»

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  • An FPGA-based processor for shogi mating problems

    Publication Year: 2002, Page(s):117 - 124
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (425 KB) | HTML iconHTML

    After the success of DEEP BLUE in computer chess, shogi, or Japanese chess is a next challenging target in artificial intelligence for game playing. The complexity and huge search space of shogi have been motivating researchers to make shogi programs, but none of them is competent enough to play against human experts. To improve the competence of shogi programs, it is a promising approach to devel... View full abstract»

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  • Population based ant colony optimization on FPGA

    Publication Year: 2002, Page(s):125 - 132
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (502 KB) | HTML iconHTML

    We propose to modify a type of ant algorithm called Population based Ant Colony Optimization (P-ACO) to allow implementation on an FPGA architecture. Ant algorithms are adapted from the natural behavior of ants and used to find good solutions to combinatorial optimization problems. General layout on the FPGA and algorithmic description are covered The most notable achievements featured in this pap... View full abstract»

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  • Clustered programmable-reconfigurable processors

    Publication Year: 2002, Page(s):134 - 141
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (537 KB) | HTML iconHTML

    In order to pose a successful challenge to conventional processor architectures, reconfigurable computing systems must achieve significantly better performance than conventional programmable processors by both greatly reducing the number of clock cycles required to execute a wide range of applications and achieving high clock rates when implemented in deep-submicron fabrication technologies. In th... View full abstract»

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  • Implementing logic in FPGA memory arrays: heterogeneous memory architectures

    Publication Year: 2002, Page(s):142 - 147
    Cited by:  Papers (6)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB) | HTML iconHTML

    It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the sto... View full abstract»

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  • Optimising and adapting high-level hardware designs

    Publication Year: 2002, Page(s):150 - 157
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (499 KB) | HTML iconHTML

    This paper presents a novel approach that focuses on rapid development and maintenance of optimised hardware designs using a high-level parallel language. We use an existing timing model that states, for instance, that every assignment executes in one clock cycle. This strict timing model gives users control over design scheduling, such as managing the number of cycles and cycle time. Our main con... View full abstract»

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  • Floating-point bitwidth analysis via automatic differentiation

    Publication Year: 2002, Page(s):158 - 165
    Cited by:  Papers (10)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    Automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value in order to minimise the circuit area and to improve efficiency of the respective arithmetic operations, while satisfying user-defined numerical constraints. We present a novel approach to bitwidth- or... View full abstract»

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  • DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

    Publication Year: 2002, Page(s):166 - 173
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstracti... View full abstract»

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  • HIDE: a logic based hardware intelligent description environment

    Publication Year: 2002, Page(s):174 - 180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB) | HTML iconHTML

    This paper presents a high-level hardware description environment based on the logic programming language Prolog, called HIDE. The latter has been designed in an attempt to address the problem of abstract hardware design and hardware efficiency. HIDE provides more abstract hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog... View full abstract»

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