2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

16-18 Dec. 2002

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  • 2002 IEEE International Conference on Field-Programmable Technology (FPT). Proceedings (Cat. No.02EX603)

    Publication Year: 2002
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  • Author index

    Publication Year: 2002, Page(s):457 - 459
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    Freely Available from IEEE
  • The effect of cluster packing and node duplication control in delay driven clustering

    Publication Year: 2002, Page(s):227 - 233
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB) | HTML iconHTML

    Although delay driven clustering algorithms can optimize circuit delay, they usually result in huge area increase. We present a node duplication control strategy along with a simple packing algorithm that greatly reduce the area penalty with a very small degradation in performance. We use the Quartus Design System from Altera to test our algorithm for a set of MCNC benchmark circuits. The results ... View full abstract»

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  • On-board satellite image compression using reconfigurable FPGAs

    Publication Year: 2002, Page(s):306 - 310
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB) | HTML iconHTML

    Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired... View full abstract»

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  • Synthesizing datapath circuits for FPGAs with emphasis on area minimization

    Publication Year: 2002, Page(s):219 - 226
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB) | HTML iconHTML

    Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, typically contain a greater portion of highly regular datapath logic. Datapath synthesis algorithms preserve these regular structures, so they can be exploited by packing, placement, and routing tools for speed or density. Typical datapath synthesis algorithms, however, sacrifice area to gain regulari... View full abstract»

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  • Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs

    Publication Year: 2002, Page(s):356 - 359
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    Symmetric FIR filters, which provide linear phases, are frequently used in digital signal processing. This paper presents the design and implementation of a novel architecture for symmetric FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of processing signal boundaries, which occurs in finite length signal processing (e.g. image processing). Bas... View full abstract»

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  • Speedup analysis in simulation-emulation co-operation

    Publication Year: 2002, Page(s):394 - 398
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB) | HTML iconHTML

    This paper presents an analytical approach to estimate the speedup in a simulation-emulation cooperation environment. The speedup of this approach as compared with the speedup of a pure simulation is analyzed. Also, an analysis of the speedup is given when different types of application instructions are utilized. The analysis is based on using both Verilog and VHDL. The results show that when only... View full abstract»

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  • The next big leap in reconfigurable systems

    Publication Year: 2002, Page(s):17 - 22
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (425 KB) | HTML iconHTML

    The age of adaptive computing is upon us, empowering the engineering community with the next big leap in computing; one in which algorithmic elements are mapped directly on to dynamic hardware resources to create the exact hardware needed for a task, clock cycle by clock cycle. The outcome of this powerful concept is a computing platform that combines the best of hardware and software into a power... View full abstract»

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  • Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing

    Publication Year: 2002, Page(s):302 - 305
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (290 KB) | HTML iconHTML

    Implementation of shortest path algorithm in FPGA has been recently proposed for solving the network routing problem. This paper discusses the architecture and implementation of shortest path algorithms for Floyd-Warshall algorithm and the parallel implementation of Bellman-Ford algorithm in the Binary Relation Inference Network architecture. There are significant differences in the performance of... View full abstract»

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  • Energy efficiency of FPGAs and programmable processors for matrix multiplication

    Publication Year: 2002, Page(s):422 - 425
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB) | HTML iconHTML

    Advances in their technologies have positioned FPGAs and embedded processors to compete with digital signal processors (DSPs). In this paper, we evaluate the performance in terms of both latency and energy-efficiency of FPGAs, embedded processors, and DSPs in multiplying two n × n matrices. As specific examples, we have chosen a representative of each type of device. Our results show that th... View full abstract»

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  • Power-aware technology mapping for LUT-based FPGAs

    Publication Year: 2002, Page(s):211 - 218
    Cited by:  Papers (22)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (553 KB) | HTML iconHTML

    We present a new power-aware technology mapping technique for LUT-based FPGAs which aims to keep nets with high switching activity out of the FPGA routing network and takes an activity-conscious approach to logic replication. Logic replication is known to be crucial for optimizing depth in technology mapping; an important contribution of our work is to recognize the effect of logic replication on ... View full abstract»

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  • Development framework for firewall processors

    Publication Year: 2002, Page(s):352 - 355
    Cited by:  Papers (3)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (325 KB) | HTML iconHTML

    High-performance firewalls can benefit from the increasing size, speed and flexibility of advanced reconfigurable hardware. However direct translation of conventional firewall rules in a router-based rule set often leads to inefficient hardware implementation. Moreover, such lowlevel description of firewall rules tends to be difficult to manage and to extend. We describe a framework, based on the ... View full abstract»

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  • A method of implementing bit-serial LDI ladder filters in FPGAs using JBits

    Publication Year: 2002, Page(s):433 - 436
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB) | HTML iconHTML

    A simulated annealing design method for low hardware cost bit-serial Lossless Discrete Integrator (LDI) recursive digital filter implementations using Field Programmable Gate Arrays (FPGAs) with JBits™ is presented. This method jointly minimizes the magnitude frequency response error and the filter hardware cost. The next-neighbor connectivity of bit-serial systems is exploited to create a p... View full abstract»

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  • The diversity study of AES on FPGA application

    Publication Year: 2002, Page(s):390 - 393
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    In the applications of AES, the long-term robustness/reliability during the period of operation should be taken into serious considerations. From such considerations, one may initiate the requirements of the design for diversity against break through from outside. In system design, the use of reconfigurable FPGA can provide higher level of flexibility. In this paper, the proposed system uses diffe... View full abstract»

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  • Dynamic reconfiguration for the common key encryption using FPGA

    Publication Year: 2002, Page(s):378 - 381
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB) | HTML iconHTML

    This paper introduces a new encryption method for a block cipher. To keep the ciphertext safe, traditional methods usually use secret keys in simple fixed logic operations. To break the cipher, cryptanalysis has been developed. They use stochastic characteristics such as differential and linear relationships between the input and output data. Encryption algorithms must be secure against these anal... View full abstract»

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  • Programmed solutions: the step beyond programmed logic [computer architecture]

    Publication Year: 2002, Page(s):13 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB) | HTML iconHTML

    The task of computer architecture is to match a user application with a base technology. This match is realized by implementing an interpreter of some representation of the application with an efficient realization, measured in cost (area), time (performance) and power. As silicon technology becomes increasingly limited by interconnects, more efficient cellular computers are attractive. Indeed lar... View full abstract»

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  • Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards

    Publication Year: 2002, Page(s):298 - 301
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB) | HTML iconHTML

    In rapid prototyping system application, any large digital circuit can be implemented onto Multi-FPGA Board(MFB). Key MFB architectural feature is its inter-FPGA connections consisting of fixed connections(FC) i.e. FPGA-FPGA connections and programmable connections(PC) i.e. FPGA-programmable switch like FPID-FPGA. MFBs consisting of both the types of connections are known as hybrid MFBs. Since, PC... View full abstract»

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  • Implementing logic in FPGA memory arrays: heterogeneous memory architectures

    Publication Year: 2002, Page(s):142 - 147
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (387 KB) | HTML iconHTML

    It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the sto... View full abstract»

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  • Delivering error detection capabilities into a field programmable device: the HORUS processor case study

    Publication Year: 2002, Page(s):418 - 421
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (346 KB) | HTML iconHTML

    Designing a complete SoC or reuse SoC components to create a complete system is a common task nowadays. The flexibility offered by current design flows offers the designer an unprecedented capability to incorporate more and more demanded features like error detection and correction mechanisms to increase the system dependability. This is especially true for programmable devices, were rapid design ... View full abstract»

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  • A technology mapping algorithm for CPLD architectures

    Publication Year: 2002, Page(s):204 - 210
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB) | HTML iconHTML

    In this paper, we propose a technology mapping algorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase we propose a look-up-table (LUT) based mapping algorithm. We will take advantage of existing LUT mapping algorithms for area and depth minimization. Benchmark results show that our algorithm ... View full abstract»

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  • Resource-aware run-time elaboration of behavioural FPGA specifications

    Publication Year: 2002, Page(s):68 - 75
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (495 KB) | HTML iconHTML

    The Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned,... View full abstract»

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  • Image fusion for uninhabited airborne vehicles

    Publication Year: 2002, Page(s):348 - 351
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (343 KB) | HTML iconHTML

    In image fusion, information from a set of images is extracted and then combined intelligently to form a new composite image with extended information content. The original data may come from different viewing conditions (bracketed focus or exposure) or various sensors (visible and infrared or a cat scan and magnetic resonance imagery). Uninhabited Airborne Vehicles (UAVs) often have visible, infr... View full abstract»

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  • FPGA implementation of MFNN for image registration

    Publication Year: 2002, Page(s):364 - 367
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (299 KB) | HTML iconHTML

    The multilayer feedforward neural network (MFNN) is modified to simplify hardware realization and at the same time retain the accuracy of detection. The results obtained have been found to be comparable to the software simulation algorithm which is used as a test base. The MFNN implementation involves low hardware complexity, good noise immunity and fast circuitry. View full abstract»

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  • Technology research and development in Hong Kong: hype or reality

    Publication Year: 2002
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (167 KB) | HTML iconHTML

    Looks at the development of innovation and technology funding, infrastructure and achievements in Hong Kong in the past few years, and examine the potential areas where Hong Kong can excel and be a significant contributor to technology development. Comparison will be drawn from Finland, an economy of a size and GDP very similar to that of Hong Kong. View full abstract»

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  • Logic synthesis of multi-output functions for PAL-based CPLDs

    Publication Year: 2002, Page(s):429 - 432
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent ... View full abstract»

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