2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

16-18 Dec. 2002

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  • 2002 IEEE International Conference on Field-Programmable Technology (FPT). Proceedings (Cat. No.02EX603)

    Publication Year: 2002
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    Freely Available from IEEE
  • Author index

    Publication Year: 2002, Page(s):457 - 459
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    Freely Available from IEEE
  • Speedup analysis in simulation-emulation co-operation

    Publication Year: 2002, Page(s):394 - 398
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB) | HTML iconHTML

    This paper presents an analytical approach to estimate the speedup in a simulation-emulation cooperation environment. The speedup of this approach as compared with the speedup of a pure simulation is analyzed. Also, an analysis of the speedup is given when different types of application instructions are utilized. The analysis is based on using both Verilog and VHDL. The results show that when only... View full abstract»

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  • Logic synthesis of multi-output functions for PAL-based CPLDs

    Publication Year: 2002, Page(s):429 - 432
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent ... View full abstract»

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  • The diversity study of AES on FPGA application

    Publication Year: 2002, Page(s):390 - 393
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    In the applications of AES, the long-term robustness/reliability during the period of operation should be taken into serious considerations. From such considerations, one may initiate the requirements of the design for diversity against break through from outside. In system design, the use of reconfigurable FPGA can provide higher level of flexibility. In this paper, the proposed system uses diffe... View full abstract»

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  • Implementation of an FPGA based accelerator for virtual private networks

    Publication Year: 2002, Page(s):34 - 41
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB) | HTML iconHTML

    Virtual Private Networks (VPN) are becoming increasingly popular network architectures for corporate networks. As VPNs are built on the Internet infrastructure, the data exchange among different local area networks will be passed through the Internet and thus can be easily eavesdropped, masqueraded, etc. Therefore, certain security measures must be used to deal with these privacy issues. The Inter... View full abstract»

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  • Reconfigurable hardware control software using anonymous libraries

    Publication Year: 2002, Page(s):426 - 428
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    This work extends RHCS with the capability to link to additional libraries at runtime just by specifying the libraries' filenames. The software components defined in the libraries are made available to the system by means of prototypes. By retaining the abstract interfaces from RHCS we are now able to dynamically compose a complete control framework at runtime without referring to any implementati... View full abstract»

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  • The feasibility study of designing a FPGA multiplier-core on finite field

    Publication Year: 2002, Page(s):386 - 389
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    In digital system development, the CPLD/FPGA is usually used to implement basic function blocks for the purposes of testing, integration and IP proof. The advantages of CPLD/FPGA are high efficiency, flexibility and easy reconfiguration. Taking AES as an example, this application needs more flexible transformations to design for diversity. In order to meet such requirements without declining the p... View full abstract»

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  • Real-time packet editing using reconfigurable hardware for active networking

    Publication Year: 2002, Page(s):26 - 33
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB) | HTML iconHTML

    An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, actio... View full abstract»

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  • Energy efficiency of FPGAs and programmable processors for matrix multiplication

    Publication Year: 2002, Page(s):422 - 425
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB) | HTML iconHTML

    Advances in their technologies have positioned FPGAs and embedded processors to compete with digital signal processors (DSPs). In this paper, we evaluate the performance in terms of both latency and energy-efficiency of FPGAs, embedded processors, and DSPs in multiplying two n × n matrices. As specific examples, we have chosen a representative of each type of device. Our results show that th... View full abstract»

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  • Efficient single-chip implementation of SHA-384 and SHA-512

    Publication Year: 2002, Page(s):311 - 314
    Cited by:  Papers (26)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algo... View full abstract»

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  • Synthesizing datapath circuits for FPGAs with emphasis on area minimization

    Publication Year: 2002, Page(s):219 - 226
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB) | HTML iconHTML

    Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, typically contain a greater portion of highly regular datapath logic. Datapath synthesis algorithms preserve these regular structures, so they can be exploited by packing, placement, and routing tools for speed or density. Typical datapath synthesis algorithms, however, sacrifice area to gain regulari... View full abstract»

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  • Field modifiable architecture with FPGAs and its design methodology

    Publication Year: 2002, Page(s):382 - 385
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB) | HTML iconHTML

    In the age of highly integrated system LSIs, the problem of design methodologies with short time-to-market and higher re-programmability after the chip fabrications has acquired great importance. Although a pure FPGA system is one of the solutions, it cannot give sufficient performance in many real-time applications due to its lower performance and higher power dissipation compared to ASICs. Inste... View full abstract»

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  • Area and time efficient implementations of matrix multiplication on FPGAs

    Publication Year: 2002, Page(s):93 - 100
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (509 KB) | HTML iconHTML

    We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the previous designs and our design are 14.45, 4.93, and 2.35, respe... View full abstract»

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  • Debug methods for hybrid CPU/FPGA systems

    Publication Year: 2002, Page(s):243 - 250
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB) | HTML iconHTML

    The combining of one or more CPU's and an FPGA fabric on the same die is growing in popularity. Such programmable system-on-chip (PSOC) systems promise performance and development time advantages over conventional technology. In a PSOC design, design errors may occur in many different places - the design of the CPU, the embedded software, the FPGA-based parts of the design, or the interfaces betwe... View full abstract»

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  • An FPGA-based processor for shogi mating problems

    Publication Year: 2002, Page(s):117 - 124
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (466 KB) | HTML iconHTML

    After the success of DEEP BLUE in computer chess, shogi, or Japanese chess is a next challenging target in artificial intelligence for game playing. The complexity and huge search space of shogi have been motivating researchers to make shogi programs, but none of them is competent enough to play against human experts. To improve the competence of shogi programs, it is a promising approach to devel... View full abstract»

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  • The next big leap in reconfigurable systems

    Publication Year: 2002, Page(s):17 - 22
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (425 KB) | HTML iconHTML

    The age of adaptive computing is upon us, empowering the engineering community with the next big leap in computing; one in which algorithmic elements are mapped directly on to dynamic hardware resources to create the exact hardware needed for a task, clock cycle by clock cycle. The outcome of this powerful concept is a computing platform that combines the best of hardware and software into a power... View full abstract»

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  • Delivering error detection capabilities into a field programmable device: the HORUS processor case study

    Publication Year: 2002, Page(s):418 - 421
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (346 KB) | HTML iconHTML

    Designing a complete SoC or reuse SoC components to create a complete system is a common task nowadays. The flexibility offered by current design flows offers the designer an unprecedented capability to incorporate more and more demanded features like error detection and correction mechanisms to increase the system dependability. This is especially true for programmable devices, were rapid design ... View full abstract»

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  • On-board satellite image compression using reconfigurable FPGAs

    Publication Year: 2002, Page(s):306 - 310
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB) | HTML iconHTML

    Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired... View full abstract»

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  • Hardware Join Java: a high level language for reconfigurable hardware development

    Publication Year: 2002, Page(s):344 - 347
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (345 KB) | HTML iconHTML

    Development of high level Hardware Description Languages (HDLs) is an integral area of research in Reconfigurable Computing (RC). There is an apparent need to enhance the development tools available and achieve more abstraction in languages to make hardware development easier for software programmers. The lack of a unified hardware/software language and difficulties in system verification are also... View full abstract»

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  • Power-aware technology mapping for LUT-based FPGAs

    Publication Year: 2002, Page(s):211 - 218
    Cited by:  Papers (22)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (553 KB) | HTML iconHTML

    We present a new power-aware technology mapping technique for LUT-based FPGAs which aims to keep nets with high switching activity out of the FPGA routing network and takes an activity-conscious approach to logic replication. Logic replication is known to be crucial for optimizing depth in technology mapping; an important contribution of our work is to recognize the effect of logic replication on ... View full abstract»

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  • Strassen's matrix multiplication for customisable processors

    Publication Year: 2002, Page(s):453 - 456
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (334 KB) | HTML iconHTML

    Strassen's algorithm is an efficient method for multiplying large matrices. We explore various ways of mapping Strassen's algorithm into reconfigurable hardware that contains one or more customisable instruction processors. Our approach has been implemented using Nios processors with custom instructions and with custom-designed coprocessors, taking advantage of the additional logic and memory bloc... View full abstract»

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  • Dynamic reconfiguration for the common key encryption using FPGA

    Publication Year: 2002, Page(s):378 - 381
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB) | HTML iconHTML

    This paper introduces a new encryption method for a block cipher. To keep the ciphertext safe, traditional methods usually use secret keys in simple fixed logic operations. To break the cipher, cryptanalysis has been developed. They use stochastic characteristics such as differential and linear relationships between the input and output data. Encryption algorithms must be secure against these anal... View full abstract»

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  • The hot decade of field programmable technologies

    Publication Year: 2002, Page(s):3 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB) | HTML iconHTML

    A historical review of the chip industry will be provided with the emphasis on the cyclical nature between standardization direction and customization direction. The basic mechanisms of the cycle will be discussed including technology factors and marketing factors. It is concluded that the field programmable technology will play the vital role in the emerging digital consumer market by providing f... View full abstract»

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  • FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator

    Publication Year: 2002, Page(s):85 - 92
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    A system level design framework for FPGA-based DSP design is presented. The design flow utilizes System Generator, a system level tool developed by Xilinx, and links it to an "in-house" architectural synthesis tool, IRIS. Whilst System Generator allows FPGA-based Intellectual Property (IP) cores to be incorporated into the design flow, it does not address the timing and latency problems introduced... View full abstract»

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