2017 International Conference on Field Programmable Technology (ICFPT)

11-13 Dec. 2017

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  • [Front cover]

    Publication Year: 2017, Page(s): 1
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  • Hub page

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  • Session list

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  • ICFPT 2017 table of contents

    Publication Year: 2017, Page(s):1 - 8
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  • ICFPT 2017 brief author index

    Publication Year: 2017, Page(s):1 - 5
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  • ICFPT 2017 detailed author index

    Publication Year: 2017, Page(s):1 - 33
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  • The end of indexes

    Publication Year: 2017, Page(s): 1
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  • About CP

    Publication Year: 2017, Page(s): 1
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  • Frequently asked questions

    Publication Year: 2017, Page(s):1 - 6
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  • Sponsors

    Publication Year: 2017, Page(s): 1
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  • A message from the general chair and program co-chairs

    Publication Year: 2017, Page(s): 1
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  • Organising committee

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  • RBSA: Range-based simulated annealing for FPGA placement

    Publication Year: 2017, Page(s):1 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (162 KB) | HTML iconHTML

    Placement has always been the most time-consuming part in the FPGA compilation flow. Traditional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes a range-based algorithm to improve the ... View full abstract»

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  • Automatic circuit design and modelling for heterogeneous FPGAs

    Publication Year: 2017, Page(s):9 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    Contemporary FPGAs are composed of a mix of full custom and standard cell-based circuitry, organized into many heterogeneous blocks and the programmable routing. To explore new FPGA architectures, in particular those incorporating new hard blocks, we must estimate the area, power and delay of any new block of interest, and would like to do so efficiently so that many ideas can be evaluated. Unfort... View full abstract»

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  • Liquid: High quality scalable placement for large heterogeneous FPGAs

    Publication Year: 2017, Page(s):17 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1641 KB)

    Generating a configuration for an FPGA is a time consuming task. Most time is required for placement and routing. Placing one of the large Titan23 designs can take more than an hour with the placer in VPR. This is too long to allow efficient turnaround times. New placement techniques are proposed to speed up the process. LIQUID is a new fast placement prototyping technique that is based on analyti... View full abstract»

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  • Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures

    Publication Year: 2017, Page(s):25 - 31
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (274 KB) | HTML iconHTML

    Quantum computers enable a massive speed-up in calculations, thanks to the nature of quantum operations. To unlock quantum computation, a classical system infrastructure is required for the control of qubits and processing of their data. While qubits are generally operating at extremely low temperatures, the implementation of such a control interface is especially challenging for large scale syste... View full abstract»

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  • High performance serial ATA Gen3 controllers on FPGA devices

    Publication Year: 2017, Page(s):32 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (698 KB) | HTML iconHTML

    An increasing number of high performance computing applications developed on reconfigurable platforms require access to mass storage devices for storing a large amount of data. The multi-gigabit transceivers integrated in FPGA devices allow the development of a wide range of communication protocols. The Serial ATA protocol provides a solution for accessing mass storage devices at high transfer rat... View full abstract»

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  • SMEFF: A scalable memory extension fabric for FPGA

    Publication Year: 2017, Page(s):40 - 47
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    In resource-constrained FPGA systems, off-chip memory plays an important role in both prototype verification and acceleration systems for big data. As the scale of applications become increasingly large and complex, the data to be processed grows exponentially. In contrast, FPGAs provide limited memory capacity and bandwidth, severely limiting the scale and performance of prototype verification sy... View full abstract»

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  • AXI over Ethernet; a protocol for the monitoring and control of FPGA clusters

    Publication Year: 2017, Page(s):48 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (154 KB) | HTML iconHTML

    AXI over Ethernet (AXIoE) is a protocol designed to extend guaranteed in-order accesses to the memory-mapped slave registers on an FPGA to a master CPU that is located elsewhere on a local area network. AXIoE was designed for use in the Square Kilometre Array (SKA) radio telescope Central Signal Processors (CSP) to provide monitor and control functionality from a few client machines to hundreds of... View full abstract»

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  • Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory

    Publication Year: 2017, Page(s):56 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB) | HTML iconHTML

    In this paper, we propose and demonstrate a real-time ultra-fast multi-data stream processing methodology on FPGA called “SWIM” (Stream Windowing on Interleaved Memory). The method exploits the flexible on-chip block memory fabric on existing FPGA architectures to achieve ultra-low-latency and fully pipelined continuous data flow while maintaining linear spatial locality of data for ... View full abstract»

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  • HopliteRT: An efficient FPGA NoC for real-time applications

    Publication Year: 2017, Page(s):64 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB) | HTML iconHTML

    Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to enable calculation of precise upper bounds on routing latency by modifying the routing function to prioritize deflections, and by regulating the injection of packets to meet certa... View full abstract»

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  • architect: Arbitrary-precision constant-hardware iterative compute

    Publication Year: 2017, Page(s):73 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB) | HTML iconHTML

    Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed or floating point, most of which operate least-significant digit first. This results in a fundamental problem: if, after some time, the result has not converged, is this because we have not run the ... View full abstract»

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  • A state machine block for high-level synthesis

    Publication Year: 2017, Page(s):80 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (770 KB) | HTML iconHTML

    FPGAs are being deployed in datacenters to enable improved energy efficiency and application acceleration. This paper explores whether FPGA designs can be improved to make them more effective in this new role. We explore the properties of applications after high-level synthesis has been applied and note that for irregular applications, a large fraction of FPGA resources may be consumed implementin... View full abstract»

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  • An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns

    Publication Year: 2017, Page(s):88 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    The current design practices for prototyping Software Defined Radio (SDR) applications using reconfigurable FPGA platforms often rely on the reuse of Intellectual Property (IP) processing cores. This design practice usually involves stitching together these IP blocks to formulate a working system. High-level Synthesis (HLS) tools that support IP core integration often do not fully allow for captur... View full abstract»

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  • Synthesis of program binaries into FPGA accelerators with runtime dependence validation

    Publication Year: 2017, Page(s):96 - 103
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (271 KB) | HTML iconHTML

    With the emergence of readily available FPGA cloud computing platforms, ease of use for application developers becomes increasingly crucial to widespread adoption. Synthesis directly from binaries has been proposed as an option to alleviate the design burden. However, in program binaries, loop bounds and loop invariants used for memory index calculation are often compiled into runtime data stored ... View full abstract»

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