2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

In 3D integrated circuit (3D-IC), there are two or more layers of active electronic components which are integrated both vertically and horizontally. Through-silicon-via (TSV) is used as the vertical electrical connection which enables a great deal of functionality packed into a small footprint. In this work we solve the signal TSV assignment problem in 3D-IC taking thermal problem into considerat... View full abstract»

Susceptibility of modern ICs to radiation-induced faults constitutes a matter of great concern in the recent years. Particularly, the transient faults and their impact on the combinational logic remain an intriguing issue, since the evaluation of their behavior is quite significant, especially for critical systems, for the development of error-resistant techniques in design process. For an accurat... View full abstract»

Heterogeneous multicores provide alternative core types and potentially multiple voltage-frequency levels to execute workloads more efficiently. One fundamental obstacle for capitalizing their potential performance and energy gains is identifying the most appropriate configuration (core type and voltage-frequency pair) for executing the computations at hand. In this paper, we analyze an ARM big.LI... View full abstract»

This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-V_T operating lev... View full abstract»

Ultra-deep sub-micron technology is shifting the design paradigm from area optimization to power optimization. In the context of Network-on-Chip (NoC) based design, energy consumption due to data transfer among network nodes is no longer negligible. Starting from the observation that, among the two brain hemispheres around 1 out of 106synapses are active at the same time, in this paper ... View full abstract»

This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted c... View full abstract»

In the paper, the memristive two-port is defined via its constitutive relation as a two-dimensional surface in a four-dimensional space of the port charges and fluxes. It follows from six possible representations of this two-port that it can be modeled via classical two-terminal memristors/memductors, complemented by four types of memristive controlled sources, each of them being controlled by two... View full abstract»

Brightness scaling is the most common way to reduce power consumption in OLED displays. Such “dimming” is generally static, i.e. it is applied either manually by the user, or automatically by the system in correspondence of predefined battery state-of-charge conditions. This is obviously sub-optimal, because it makes brightness adaptation (i) too coarse-grain in time, and (ii) agnostic of the imag... View full abstract»

ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cas... View full abstract»

This paper presents the energy analysis of capacitive adiabatic logic (CAL) based on gap-closing MEMS devices. CAL uses variable capacitance components instead of transistor elements to have a new balance between on- and off-state losses. Ultra-low power consumption in CAL requires an energy efficient way for charging and discharging of the variable capacitance. First, we investigate “pure” electr... View full abstract»

We present a silicon nanowire-based field-effect transistor biosensor with Schottky barriers for highly specific and sensitive human α-thrombin detection. The active sensor area is decorated with thrombin-binding aptamers as receptor molecules. Each sensor chip is integrated into a microfluidic device for flow-through measurements. Instantaneous detection is provided by real-time monitoring of FET... View full abstract»

Memristors have extended their influence beyond memory to logic and in-memory computing. Memristive logic design, the methodology of designing logic circuits using memristors, is an emerging concept whose growth is fueled by the quest for energy efficient computing systems. As a result, many memristive logic families have evolved with different attributes, and a mature comparison among them is nee... View full abstract»

We describe an analysis of the main process parameters variability involved in electrical and optical output characteristics of an optical sensor integrating a standard silicon-based NWell in p-epitaxial substrate photodiode and an UV/IR blocking interference filter. This study is done with TCAD simulation following a standard 0.18 μm high voltage CMOS technology fabrication process. The TCAD simu... View full abstract»

In this paper, we present a simple analytical delay model for memristive memory cells. The output voltage evolution is obtained analyzing the charge-flux dynamics when a voltage ramp is applied to the input. From this evolution, the propagation delay is calculated. The model is validated using the VTEAM memristor model for different input rise time values of the applied ramp. The proposed model ca... View full abstract»

Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising f... View full abstract»

Redox-based resistive switching devices can be switched between a high resistance state and a low resistance state in a reversible manner. An important requirement is the stable operation between these two states for a high amount of switching cycles. In this work the switching dynamics of these devices are investigated by means of device simulation. Hereby, we discuss the conditions for which a f... View full abstract»

As the importance of the thermal issues in the design of multiprocessor systems increases, it becomes mandatory to analyze the thermal effects and the thermal management techniques early in the design flow, ideally during the hardware emulation phase. Moreover, several scenarios (multiprocessor systems connected with photonic NoCs, 3D systems, etc.) demand a high accuracy during the thermal emulat... View full abstract»

Managing the power in highly-integrated systems on chips becomes inevitable in modern designs. Complex systems require complex power management, and it is always difficult to determine whether the designed power management is the most efficient. In our previous work, we have proposed a simplified power-management specification method at the system level of abstraction. In this paper, we propose a ... View full abstract»

In this work, we present a combined analysis on the statistical variability of threshold voltage, on-state current, and leakage current of III-V ultra-scaled MOSFETs. In addition, we analyze the sensitivity of threshold voltage to critical geometrical and process parameters variations (i.e., gate length, channel thickness, oxide thickness and channel doping). Our analysis verifies the scaling pote... View full abstract»

Application requirements along with the unceasing demand for ever-higher scale of device integration, has driven technology towards an aggressive downscaling of transistor dimensions. This development is confronted with variability challenges, mainly the growing susceptibility to time-zero and time-dependent variations. To model such threats and estimate their impact on a system's operation, the r... View full abstract»

In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of %... View full abstract»

In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional sta... View full abstract»