2017 47th European Solid-State Device Research Conference (ESSDERC)

An analysis of research in quantum nanoelectronics and nanomagnetics for beyond CMOS devices is presented. Some device proposals and demonstrations are reviewed. Based on that, trends in this field are identified. Principles for development of competitive computing technologies are formulated. Results of beyond-CMOS circuit benchmarking are reviewed. View full abstract»

Storage class memories (SCMs); for instance, (STT-)MRAM, ReRAM, PRAM, and 3D XPoint, have much attention from storage systems. Each SCM has different characteristics, such as read/write latency, endurance, and bit cost. For example, MRAM has short latency and high endurance, but its cost is high. In contrast, ReRAM, PRAM, and 3D XPoint have lower endurance, but their cost is lower than MRAM. From ... View full abstract»

The repeatability of set/reset errors has been investigated in 40nm TaOx based ReRAM cells. Errors of the Low Resistance State (LRS) in specific cells are observed repeatedly, and such cells are recovered by DC read operation. When error cells are recovered, the LRS cell current of the recovered cells shows a sudden jump up to large cell current in certain set cycles. Then, the High Resistance Sta... View full abstract»

This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of ... View full abstract»

In this work, we investigate the robustness of 1-transistor-1-resistor (1T1R) synaptic array to implement a low-precision neural network. The experimental results on 1 kb HfOx-based RRAM array show a large on/off ratio (i.e. > 105×) and 5 stable resistance states can be reliably achieved with 10× window between adjacent two states. As the RRAM has the resista... View full abstract»

Compact modeling has evolved considerably since SPICE was announced to the world in 1973. Many challenging model formulation problems have been solved, and model code itself has changed from being tightly integrated within simulators to being defined in a stand-alone manner. Decades of research led to the former, Verilog-A enabled the widespread adoption of the latter. This paper reviews key steps... View full abstract»

SPlCE-compatible modeling with generalized lumped devices is used to simulate the spatial and time dependence of photogenerated carriers with standard circuit simulators. Equivalent voltages and currents are used in place of minority carrier excess concentrations and minority carrier currents respectively. The initial light-induced excess carrier concentration in silicon is accounted by means of d... View full abstract»

This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key parameters of the simplified EKV model. The latter are extracted from the measured transfer characteristics at each TID. Despite the very few para... View full abstract»

Low-frequency noise characteristics have been investigated in arrays of 14 nm gate-all-around vertical silicon junction-less nanowire transistors. Extensive measurements have been performed to study the evolution of the 1/f noise as a function of bias for nanowire arrays with different nanowire diameters and several numbers of nanowires in parallel. Measured drain current noise can be explained we... View full abstract»

Single gate oxide defects in strongly scaled Tunneling Field-Effect Transistors with an inverse subthreshold slope well below 60 mV/decade are investigated by Random Telegraph Signal (RTS) noise measurements. The cause for RTS noise are electrons being captured in and released from individual defects in the gate oxide. Under the assumption that elastic tunneling is the underlying capture and emiss... View full abstract»

Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of t... View full abstract»

In this paper we present the recent advances in the understanding of microscopic mechanisms driving the resistive switching in ReRAM devices using ab initio theoretical methods. We highlight the complex interplay between interface reactions and charge injection in the generation of oxygen Frenkel pairs during the forming step. Energy barrier calculations suggest that the formation/destruction of t... View full abstract»

Surface roughness causes random shifts in the lowest sub-band level around its ideal position. This gives rise to tail states of an otherwise step-like DOS of the 2D electron gas in the channel. These tail states cause a gradual onset of tunneling in a TFET with vertical tunnel paths and degrade the sub-threshold swing. The impact of roughness of the semiconductor/oxide interface on the transfer c... View full abstract»

In this paper, we study the impact of different device architectures and material properties on the performance of two-dimensional tunnel FETs (2D TFETs). We show that single-gate (SG) device architecture in case of monolayer and few layers two-dimensional materials perform better than doublegate (DG) architecture. Due to sharper band bending at the tunneling junction, SG device offers shorter tun... View full abstract»

The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations an... View full abstract»

This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design paramet... View full abstract»

This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations ... View full abstract»

The cut-off frequencies of silicon-germanium hetero-junction bipolar transistors (SiGe HBTs) have entered the THz range at the cost of high current density and relatively low breakdown voltages. Typically, the common-emitter breakdown voltage with open base (BVCEO) is used to indicate the allowed breakdown voltage related operation limit. However, an open base (i.e. an infinite source impedance) i... View full abstract»

The underlying variability in the ReRAM device operation, while undesired in many applications, can be advantageous for hardware security primitives. ReRAM devices also come with the advantage of having non-linear multi-state operation. By comparison with previous reported ReRAM PUFs, which utilized spatial variations in the devices' binary ON/OFF states, we proposed to use sneak path currents and... View full abstract»

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an... View full abstract»

We present a study on multi-gate field-effect transistors that allow adjusting the potential landscape in semiconducting nanowires/tubes on the nanoscale. To this end, a damascenelike process is employed that allows fabricating a large number of gate structures that are contacted individually and exhibit lengths and inter-gate distances well below 10nm enabling to realize potential landscapes with... View full abstract»

A compact model for the low and high resistance state conduction characteristics of electroformed capacitors with hexagonal boron nitride (A-BN) as insulator material and with multi-layer graphene and metal electrodes is presented. The model arises from an approximation of the expression for multi-filamentary electron transport with parabolic shaped constrictions. The model takes into account the ... View full abstract»

A new analytical static drain current model based on the WKB approximation has been developed for Schottky-Barrier CNTFETs. Electron scattering by acoustic and optical phonons in the channel has been taken into account. By using a simple approximation of both the Fermi-Dirac distribution function and transmission probability, an analytical expression for the drain current in the Landauer-Bü... View full abstract»

In this work, we present a circuit model of diffusive spintronic devices capable of capturing the effects of both electric and magnetic fields. Starting from a modified version of the well-established drift-diffusion equations, we derive general equivalent circuit models of semiconducting/metallic nonmagnets and metallic ferromagnets. In contrast to other models that are based on steady-state tran... View full abstract»