2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems

22-24 June 2017

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Displaying Results 1 - 25 of 134
  • [Front cover]

    Publication Year: 2017, Page(s): c1
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  • [Title page]

    Publication Year: 2017, Page(s):1 - 2
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  • Preface

    Publication Year: 2017, Page(s):3 - 4
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  • International programme committee

    Publication Year: 2017, Page(s):5 - 6
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  • Table of contents

    Publication Year: 2017, Page(s):7 - 12
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  • General invited papers

    Publication Year: 2017, Page(s): 1
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  • Emerging sigma-delta modulation techniques for an efficient digitization in the Internet of Things

    Publication Year: 2017, Page(s):15 - 16
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    This talk gives an overview of ΣΔ modulation techniques for the efficient implementation of analog/digital interfaces in IoT devices. Main design challenges derived from their integration in deep nanometer CMOS are identified, and state-of-the-art circuits and systems solutions are discussed. Diverse application scenarios, ranging from ultra-low-power biomedical devices to ultra-wide-band wireless... View full abstract»

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  • High-performance silicon photonics platform for low-power photonic integrated circuits

    Publication Year: 2017, Page(s):17 - 18
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (637 KB) | HTML iconHTML

    High-performance Silicon photonics platform based on an advanced Si CMOS technology is a key to produce low-power integrated photonic chips for the optical interconnect in data transmission. The state-of-the-art Silicon photonics technology has been developed by using 40 nm CMOS technology. Key features are highly reproducible optical devices and high-quality epitaxial growth Ge for photodetectors... View full abstract»

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  • Introduction of Analog Front End IC used in sensing system

    Publication Year: 2017, Page(s):19 - 20
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    The electronic sensing system consists of “Sensor”, “Analog Front End (AFE)” block, and “Digital Signal Processor (DSP)” blocks. Here explains about required performances and functions of “AFE” Device, which deals with different application and different frequency range with two types of examples (“Electro-chemical Gas Sensing” and “Residual Current-Circuit-Breaker”). View full abstract»

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  • The future of CMOS: More Moore or the next big thing?

    Publication Year: 2017, Page(s):21 - 26
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    This paper discusses the industrial and research status of CMOS and CMOS-like commercial and emerging technologies. Effects of scaling on transistor cost, max. system complexity and performance are discussed. Performance of state-of-the-art CMOS VLSI systems is power-constrained. To discuss various existing and emerging technologies, a model of an abstract, technology-independent ideal switch is p... View full abstract»

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  • New trend of analog systems

    Publication Year: 2017, Page(s): 1
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  • Integrated CMOS ADC — Tutorial review on recent hybrid SAR-ADCs

    Publication Year: 2017, Page(s):29 - 34
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (866 KB) | HTML iconHTML

    Recently, SAR-ADC architecture is often used as an integrated ADC architecture in VLSI chip. The advantage of SAR ADC is the non-necessity of high-gain OP amps, low power consumption features, and it's suitability to fine process. On the other hand, disadvantage with simple SAR architecture, however, is its difficulty to achieve high-sampling frequency and/or high SNDR. There are many proposals on... View full abstract»

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  • Sensor/RF digitization for IoT-applications using all-digital-very-scalable-ADC TAD

    Publication Year: 2017, Page(s):35 - 40
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (529 KB) | HTML iconHTML

    As sensor and RF digitization for IoT-applications, this paper presents a concept of the digitization based on the all-digital-ADC TAD (Time A/D converter) as a both scalable and durable analog-interface using all-digital time-domain processing. TAD consists of all-digital circuits such as a Fin-supply-controlled ring-shaped pulse-delay-line (RDL) with 32 (in 0.65μm-CMOS), 64 (0.18μm-CMOS) or 128 ... View full abstract»

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  • SI/PI/EMI simulation techniques and application to automotive electronic design issues

    Publication Year: 2017, Page(s):41 - 44
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (797 KB) | HTML iconHTML

    In this paper, SI/PI/EMI design issue is addressed. For these years, we have dealt with a variety of simulation methods for the Chip/Package/Board co-designed systems. In this aspect, the efficient verification tool for the design, namely the fast and high-precision simulator has been demanded. Here, we consider the efficient one from the viewpoints of the algorithm and hardware acceleration. Firs... View full abstract»

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  • A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode

    Publication Year: 2017, Page(s):45 - 49
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (189 KB) | HTML iconHTML

    A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation mode using ring amplifier and SAR quantizer. Proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order modulator in 90nm CMOS technology. Simulated SNDR o... View full abstract»

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  • A delta-sigma DAC with feedforward jitter-shaper reducing jitter noise

    Publication Year: 2017, Page(s):50 - 54
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    This paper present a novel delta-sigma digital-to-analog converter with a jitter shaper that has feedforward passes to reduce the noise caused by clock jitter. Intermodulation between the quantization noise and clock jitter produces wide spectrum noise, which degrades the signal-to-noise ratio (SNR) of the delta-sigma DAC. Since the accuracy of the delta-sigma DAC is determined by the jitter, it c... View full abstract»

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  • A design method of low frequency universal filter employing MOCCIIs

    Publication Year: 2017, Page(s):55 - 60
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    In this paper, a design method of a low-frequency universal current-mode filter employing second generation multiple output current conveyors with current amplification function is proposed. Low-frequency filters for biological signals need large capacitances. To realize a large apparent capacitance on a chip, the current amplification factor of the second generation multiple output current convey... View full abstract»

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  • A high precision vernier type delta-sigma time to digital converter

    Publication Year: 2017, Page(s):61 - 66
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (818 KB) | HTML iconHTML

    In this paper, we propose a high precision vernier type delta-sigma time to digital converter (TDC) architecture. The time resolution of conventional delta-sigma TDC that has a delay stage consists of a delay element and three multiplexers is strongly dependent on the delay time for a delay element used in the delay stage and the measurement time. However, the delay time is limited by the compleme... View full abstract»

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  • A simple current reference with low sensitivity to supply voltage and temperature

    Publication Year: 2017, Page(s):67 - 72
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (411 KB) | HTML iconHTML

    We propose a simple current reference circuit with low power supply voltage dependence and low temperature coefficient by combining output currents of conventional current mirror and Nagata current source. Detailed analysis and design procedure are presented. Preliminary test chip measurement results are also represented. Temperature dependence of the output current was compensated by synthesizing... View full abstract»

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  • An application for tree structure NSDEM to a directivity speaker with amplitude controlling a digitally direct driven speaker

    Publication Year: 2017, Page(s):73 - 78
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    Tree-structure NSDEM method has been proposed as a method to suppress and reduce the circuit size due to the number of sub-speaker of a digitally direct driven speaker. In this study, we applied this tree structure NSDEM to a directivity speaker system using digitally direct drive method, and simulation and actual measurement are carried out and the results are presented. View full abstract»

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  • Applying negative feedback to improve linearity and input property of analog CMOS transresistor

    Publication Year: 2017, Page(s):79 - 83
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    The paper presents an idea of improving both linearity and input impedance of a simple low-voltage CMOS current to voltage converter (C-V converter). The idea is based on using negative feedback around the whole converter. Applying the proposed feedback allows us to make smaller the converter nonlinearities and reduce the converter input resistance. Necessary condition to achieve this aim is to di... View full abstract»

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  • Comparator design for linearized statistical flash A-to-D converter

    Publication Year: 2017, Page(s):84 - 89
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    We proposed a linearization technique with dynamic element matching for stochastic flash A-to-D converters (SFADCs), and estimated that 6-bit SFADC can be realized by using about 1,000 comparators through system level simulations. In this paper, we present circuit level design of the linearized SFADC. First, we discuss the difference between requirements of comparators for conventional flash ADC a... View full abstract»

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  • Experimental study of the oscillation mode of the coupled oscillator ORIGAMI for TDC

    Publication Year: 2017, Page(s):90 - 94
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1157 KB) | HTML iconHTML

    Based on the experimental results of the oscillation mode of the coupled oscillator, ORIGAMI, which is used as a high-resolution time-to-digital converter(TDC), modified ORIGAMI oscillator and a new coding scheme, 2 dimensional center of gravity code (2D-CGC), are proposed and discussed in detail. To examine the performance of the proposed technique, simulation results are shown, where the 0.18 μm... View full abstract»

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  • Improvement technique of tuning range for local-feedback MOS transconductor

    Publication Year: 2017, Page(s):95 - 100
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (375 KB) | HTML iconHTML

    A local-feedback transconductor (LFB OTA) is a linear OTA operating in a saturation region. In addition, the LFB OTA operating in a subthreshold region, whose transfer characteristics are expressed by a sinh function, is utilized for low-power and low-transconductance linear OTAs. However, the LFB OTA has a limit of a tuning range of a transconductance because of a local-feedback structure. To imp... View full abstract»

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  • Low-distortion low-power MOSFET-C filter design method

    Publication Year: 2017, Page(s):101 - 104
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    This paper proposes a novel approach to realize highly linear MOSFET-C filters. The proposed method is combination of the methods in [7] and [8]. The method requires two control voltages which are applied to gate terminals of MOSFETs operating in non-saturation region while the methods in [8] does more than two control voltages. Requirement of several control voltages might cause much distortion a... View full abstract»

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