27th ACM/IEEE Design Automation Conference

24-28 June 1990

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  • 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • A heuristic algorithm for the fanout problem

    Publication Year: 1990, Page(s):357 - 360
    Cited by:  Papers (46)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    An algorithm is presented to optimally distribute a signal to its required destinations. The choice of the buffers and the topology of the distribution tree depends on the availability of different strength gates and on the load and the required times at the destination. Since the area-constrained fanout problem is NP-complete and area is not a major consideration in present high-density designs, ... View full abstract»

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  • Algorithms for library-specific sizing of combinational logic

    Publication Year: 1990, Page(s):353 - 356
    Cited by:  Papers (35)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Examined is a problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary input to the primary output. It is shown that, if the Boolean network has a tree topology, there exists a pseudo-polynomial time algorithm for finding the optimal solution to this problem. A backtrac... View full abstract»

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  • Delay and area optimization in standard-cell design

    Publication Year: 1990, Page(s):349 - 352
    Cited by:  Papers (38)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A heuristic approach to the optimal selection of standard cells in VLSI circuit design is presented. A cell library is composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, one selects the best templates from the cell library to minimize the total area... View full abstract»

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  • A fault analysis method for synchronous sequential circuits

    Publication Year: 1990, Page(s):732 - 735
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    A new fault analysis method for synchronous sequential circuits is presented. Using the iterative array method, extended forward propagation and backward implication are performed, based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. Any stuck fault can be identified, even in a circuit without any initialization sequence. A fault ... View full abstract»

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  • Efficient implementation of a BDD package

    Publication Year: 1990, Page(s):40 - 45
    Cited by:  Papers (414)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. A package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation is described. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong canonical form in the ROBD... View full abstract»

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  • An object-oriented VHDL design environment

    Publication Year: 1990, Page(s):431 - 436
    Cited by:  Papers (13)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A system-level design environment (SDE) for the VHSIC hardware description language (VHDL) is presented. The object-oriented approach is used for modeling the VHDL entities, design constraints, and even design patterns. The data model and its internal schema, which are suitable for the VHDL semantics, are proposed. SDE allows a designer to reconfigure the designed schematic by binding its generic ... View full abstract»

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  • Layout synthesis of MOS digital cells

    Publication Year: 1990, Page(s):241 - 245
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed View full abstract»

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  • Timing driven placement using complete path delays

    Publication Year: 1990, Page(s):84 - 89
    Cited by:  Papers (78)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A methodology for standard cell or gate array designs is described. A new approach is introduced whereby the placement process is divided into a global step and a detailed step. The timing drive placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during pla... View full abstract»

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  • Logic optimization algorithm by linear programming approach

    Publication Year: 1990, Page(s):345 - 348
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A new logic synthesis algorithm for reducing the delay time with the least increase of gate is presented. This algorithm uses a linear programming approach and makes it possible for delay and gate optimization to be achieved simultaneously from the global point of view. Therefore, this new algorithm prevents the generation of redundant logic arising from the delay time improvement, which is a weak... View full abstract»

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  • MISER: an integrated three layer gridless channel router and compacter

    Publication Year: 1990, Page(s):698 - 703
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    Presented is a new gridless, three-layer channel router (MISER) based on an integrated approach to routing and compaction in VLSI design. MISER partitions the input net-list into several sub-net-lists called levels and forms a level-graph. This level-graph is used to guide the routing and compaction process. Compaction is done immediately after each level is routed. Experimental results show that ... View full abstract»

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  • Automatic test generation using quadratic 0-1 programming

    Publication Year: 1990, Page(s):654 - 659
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    In an unconventional digital circuit modeling technique using neural nets proposed by the authors, the relationship between the input and output signal states of a logic gate is expressed through an energy function such that the minimum-energy states correspond to the gate's logic function. Based on these unconventional models, automatic test generation (ATG) was formulated as an energy minimizati... View full abstract»

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  • Synthesis using path-based scheduling: algorithms and exercises

    Publication Year: 1990, Page(s):450 - 455
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis they stress optimization across conditional branches. Several path-based algorithms are presented. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic ... View full abstract»

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  • PALACE: a layout generator for SCVS logic blocks

    Publication Year: 1990, Page(s):468 - 473
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    A novel approach to the automatic layout synthesis of dynamic CMOS circuits is presented. A set of logic expressions is realized in a row of cells. Taking multi-level Boolean expressions as input, logic transistors are placed and routed. Efficient solutions are achieved by permitting the variables of the expressions and by row folding. The layout is designed on a coarse grid taking timing requirem... View full abstract»

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  • An O(n1.5 log n) 1-d compaction algorithm

    Publication Year: 1990, Page(s):382 - 387
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Key algorithms and properties of 1-d IC layout compaction are presented. In particular, the spacing constraint formulation problem is mapped into the vertical visibility graph construction problem, whose time complexity is O(n log n) if element swappings are not considered. This approach generates enough constraints for the later automatic jogging purposes, while maintai... View full abstract»

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  • A variable observation time method for testing delay faults

    Publication Year: 1990, Page(s):728 - 731
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Test methodologies for delay faults usually observe output patterns at a single observation time, and the same observation time is used for all faults in the circuit under test. It is shown that use of a single observation time is not advantageous for testing delay faults, and the detection threshold can be dramatically improved by using a testing methodology that allows variable, fault-dependent,... View full abstract»

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  • A new simultaneous partitioning and chip placement approach based on simulated annealing

    Publication Year: 1990, Page(s):36 - 39
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A major issue in VLSI design is that of determining how circuit components are to be distributed among a set of chips (partitioning problem) and where these chips are to be located on a board (placement problem) in order that densely connected components are placed close together and the wiring between the chips is minimized. A new partitioning and placement approach is proposed in which these pro... View full abstract»

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  • Organized C: a unified method of handling data in CAD algorithms and databases

    Publication Year: 1990, Page(s):425 - 430
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A data management package, called Organized C, is described. The main features of this package are simple and compact declarations which translate organizations into the definitions of classes, pointers, and access functions. This method adds a new dimension to the inheritance mechanism, works with both C and C++, and is specifically useful for CAD software which often deals with large and complex... View full abstract»

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  • A design platform for the NELSIS CAD framework

    Publication Year: 1990, Page(s):146 - 149
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A design platform is a central user interface to a CAD framework. It enables information retrieval, object selection, and tool activation in a uniform and integrated fashion. A description is given of such a design platform with emphasis on the graphical metadesign data-browsing facilities. The design platform informs designers about the latest developments of their designs and simplifies interact... View full abstract»

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  • LECSIM: a levelized event-driven compiled logic simulator

    Publication Year: 1990, Page(s):491 - 496
    Cited by:  Papers (30)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    LECSIM is an efficient logic simulator which integrates the advantages of event-drive interpretive simulation and levelized compiled simulation. Two techniques contribute to the high efficiency. First, it employs the zero-delay simulation model with levelized event scheduling to eliminate most unnecessary evaluations. Second, it compiles the central event scheduler into simple local scheduling seg... View full abstract»

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  • Test function specification in synthesis

    Publication Year: 1990, Page(s):235 - 240
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A new synthesis-for-testability method is presented in which a test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as a FSM with the same number of state variables as the given object machine. The state graph of the test machine is so defined that each state is uniquely set and observed by an input sequence no longer than logk... View full abstract»

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  • A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm

    Publication Year: 1990, Page(s):77 - 83
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A new method for high-level logic synthesis is reported whose basic feature is the tight interaction and coupling of the scheduling and allocation phases providing a global direction to the synthesis. A linear-program-based allocation is proposed which uses multifunction-ALU cost estimation and iteratively drives a tree-search for scheduling. A new interconnect optimization algorithm is proposed. ... View full abstract»

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  • Design methodology management-a CAD framework initiative perspective

    Publication Year: 1990, Page(s):278 - 283
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The design of today's electronic systems involves the use of a growing number of complex CAD tools. Invoking and controlling these tools, independently or as part of a captured, multioperation flow, remains an error-prone and largely unsolved problem. This problem is the focus of the design methodology management technical subcommittee (DMMTSC) of the CAD framework initiative. The authors describe... View full abstract»

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  • Timing optimization for multi-level combination networks

    Publication Year: 1990, Page(s):339 - 344
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    A timing optimization algorithm SDLR (SYLON-DREAM level-reduction) is presented, which is used in the SYLON-DREAM logic synthesizer for speeding up combinational multilevel networks. In SDLR, gates on critical paths are identified and their level numbers counted from the inputs of the network are maximally reduced by a level-reduction procedure. Gates which are not on the critical paths are proces... View full abstract»

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  • How to prove the completeness of a set of register level design transformations

    Publication Year: 1990, Page(s):207 - 212
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The VLSI design transformations used in the kernel of any interactive design exploration tool should be correct and should, preferably, form a complete set. Completeness guarantees that any correct design for the given specification can be produced using the tool. A method of proving completeness of register level design transformations is discussed. Using this method, it is shown that a set of tr... View full abstract»

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