2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

11-13 July 2016

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Displaying Results 1 - 25 of 143
  • [Front cover]

    Publication Year: 2016, Page(s): C4
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  • [Title page i]

    Publication Year: 2016, Page(s): i
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  • [Title page iii]

    Publication Year: 2016, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2016, Page(s): iv
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  • Table of contents

    Publication Year: 2016, Page(s):v - xvi
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  • Message from the General Chairs

    Publication Year: 2016, Page(s): xvii
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  • Message from the Technical Program Chairs

    Publication Year: 2016, Page(s):xviii - xix
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  • Organizing Committee

    Publication Year: 2016, Page(s):xx - xxi
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  • Steering Committee

    Publication Year: 2016, Page(s): xxii
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  • Technical Program Committee Track Chairs

    Publication Year: 2016, Page(s): xxiii
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  • Technical Program Committee

    Publication Year: 2016, Page(s):xxiv - xxvi
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  • Additional reviewers

    Publication Year: 2016, Page(s): xxvii
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  • Keynote abstracts [3 abstracts]

    Publication Year: 2016, Page(s):xxviii - xxxii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Provides an abstract for each of the three keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Panel Discussion: Nanotechnology-Inspired Future Computing, Challenges and Opportunities

    Publication Year: 2016, Page(s): xxxiii
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  • A New Process Variation Monitoring Circuit

    Publication Year: 2016, Page(s):1 - 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (869 KB) | HTML iconHTML

    A new process variation monitoring circuit (PVMC) has been proposed in the paper. The goal is to generate a digital signal/code which (code value) will characterize the process corner. The circuit uses only metal-oxide-semiconductor (MOS) transistors to detect variation of their parameters, or process corner by generating digital signals. Process variation is detected based on variation of paramet... View full abstract»

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  • Mixed-Signal Design Using Digital CAD

    Publication Year: 2016, Page(s):6 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (267 KB) | HTML iconHTML

    The paper investigates the use of the existing CAD framework for digital circuit synthesis to design and synthesize a select set of mixed-signal functions like analog-to-digital and digital-to-analog conversions. This approach leads to fast and low cost design of technology portable system-on-chip solutions with analog interfaces. Some circuit examples for implementation of data conversion using d... View full abstract»

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  • An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation

    Publication Year: 2016, Page(s):12 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current mode receiver and is made adaptive to varying channel loss. Therefore, the need for an external termination to avo... View full abstract»

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  • FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation

    Publication Year: 2016, Page(s):18 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB) | HTML iconHTML

    There is a rapidly growing interest in the field of unmanned road vehicles across the world. To aid the traffic management of such systems, there is an urgent need to develop appropriate security protocols facilitating car-to-car and car-to-traffic controller systems. Ensuring security requires both confidentiality (will be understandable only to intended recipients) as well as authenticity (messa... View full abstract»

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  • Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware

    Publication Year: 2016, Page(s):24 - 29
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (826 KB) | HTML iconHTML

    Convolutional Neural Network (CNN) has become a successful algorithm in the region of artificial intelligence and a strong candidate for many applications. However, for embedded platforms, CNN-based solutions are still too complex to be applied if only CPU is utilized for computation. Various dedicated hardware designs on FPGA and ASIC have been carried out to accelerate CNN, while few of them exp... View full abstract»

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  • An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs

    Publication Year: 2016, Page(s):30 - 35
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (501 KB) | HTML iconHTML

    Partial reconfiguration (PR) enhances traditional FPGA-based reconfigurable embedded systems with benefits such as reduced resource requirements and increased functionality. Since fully realizing these PR benefits requires extensive PR design flow knowledge, as well as the target FPGA's low-level architectural details, PR has not yet gained widespread usage. To alleviate manual design-time effort,... View full abstract»

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  • Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees

    Publication Year: 2016, Page(s):36 - 41
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (637 KB) | HTML iconHTML

    Circuit legalization removes overlaps and keeps cell alignment with power rails while minimizing total cell displacement. Legalization is applied not only after global placement, but also after incremental optimization steps like detailed placement, gate sizing, and buffer insertion. Applying full legalization after such incremental optimizations is too time-consuming. That is why physical synthes... View full abstract»

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  • Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model

    Publication Year: 2016, Page(s):42 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (541 KB) | HTML iconHTML

    Presently, almost all timing analyses and optimization tools are based on the strategy of setup and hold time constrained flip-flop timing model. However, this is a big mismatch with the timing characteristic of the real life flip-flops, which is so called flexible flip-flop timing, in which the clock-to-Q delay of every flip-flop may vary dynamically according to its setup and hold skews. This wo... View full abstract»

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  • Synthesizing Asynchronous Circuits toward Practical Use

    Publication Year: 2016, Page(s):47 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (591 KB) | HTML iconHTML

    This work proposes a new method of synthesizing asynchronous circuits targeting its practical usability. The key contribution of this work is finding an effective technique of inter-mixing the two design principles namely handshaking based single-rail and timing annotated (i.e., delay insensitive) dual-rail of asynchronous circuits. Precisely, we propose clever ways of partitioning an input (synch... View full abstract»

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  • Next Generation Automotive Architecture Modeling and Exploration for Autonomous Driving

    Publication Year: 2016, Page(s):53 - 58
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (581 KB) | HTML iconHTML

    To support emerging applications in autonomous and semi-autonomous driving, next-generation automotive systems will be equipped with an increasing number of heterogeneous components (sensors, actuators and computation units connected through various buses), and have to process a high volume of data to percept the environment accurately and efficiently. Challenges for such systems include system in... View full abstract»

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  • Online Unusual Behavior Detection for Temperature Sensor Networks

    Publication Year: 2016, Page(s):59 - 62
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    In modern smart building climate control systems, accurate detection of unusual behavior in temperature sensors (outliers) can help reduce or prevent waste of energy consumption in a Heating, Ventilation and Air Conditioning (HVAC) system. In this work, we propose online learning-distance based outlier detection method. In the new method, we train and tune a multilayer neural network to learn a no... View full abstract»

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