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Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on

Date 11-14 March 2001

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  • Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001

    Publication Year: 2001
    Save to Project icon | Request Permissions | PDF file iconPDF (158 KB)  
    Freely Available from IEEE
  • Author index

    Publication Year: 2001 , Page(s): 219
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    Freely Available from IEEE
  • Synthesis and implementation of a signal-type asynchronous data communication mechanism

    Publication Year: 2001 , Page(s): 127 - 136
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (780 KB) |  | HTML iconHTML  

    This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-driven (“lazy”) logic must be interfaced with a time-driven (“busy”) environment. A new classification system for ACMs is introduced. The conceptual definition of the signal ACM (called simply &ldquo... View full abstract»

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  • Exploiting typical DSP data access patterns and asynchrony for a low power multiported register bank

    Publication Year: 2001 , Page(s): 4 - 14
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    CADRE (Configurable Asynchronous DSP for Reduced Energy) is a low-power asynchronous DSP (digital signal processor) architecture intended for digital mobile phone chipsets. Central to the architecture are the X and Y register banks, which supply the four processing units with the data they require and to which results are written. The register banks each require 10 read and 6 write ports to servic... View full abstract»

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  • Designing fast asynchronous circuits

    Publication Year: 2001 , Page(s): 184 - 193
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    A five-step design process for asynchronous circuits helps simplify their logic and speed their operation. First, assume that all logic gates in the control will have nearly uniform delay. Second, use the uniform delay assumption to simplify control logic. Third, lay out the chip to get wire length data. Fourth, choose a specific delay and calculate transistor widths to apply that specific delay u... View full abstract»

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  • A low-power self-timed Viterbi decoder

    Publication Year: 2001 , Page(s): 15 - 24
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    Viterbi decoders are used for decoding data encoded using convolutional forward error correction codes or data that suffers from inter-symbol interference. They occur in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital TV broadcast, CD-ROM and magnetic disk reading. This paper describes a design for a self-timed Viterbi decode... View full abstract»

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  • Efficient exact two-level hazard-free logic minimization

    Publication Year: 2001 , Page(s): 64 - 73
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (844 KB) |  | HTML iconHTML  

    This paper presents a new approach to two-level hazard free sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-free logic minimization can handle large circuits without synthesis times ranging up over thousands of seconds. The logic minimization approach presented in this paper is based on state graph exploration in conjunction wi... View full abstract»

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  • An asynchronous superscalar architecture for exploiting instruction-level parallelism

    Publication Year: 2001 , Page(s): 140 - 151
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1112 KB) |  | HTML iconHTML  

    This paper proposes an asynchronous superscalar architecture called DCAP to exploit instruction-level parallelism based on a novel dynamic instruction scheduling technique. The proposed technique not only has an efficient implementation using asynchronous micropipelines, it also minimizes the amount of hardware required for instruction scheduling when compared to standard schemes used in synchrono... View full abstract»

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  • FLEETzero: an asynchronous switching experiment

    Publication Year: 2001 , Page(s): 173 - 182
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    This paper describes a working chip, called FLEETzero, built to test an asynchronous switch fabric. The switch fabric transports 8-bit data items from any of eight sources to any of eight destinations. Measured throughput corresponds to approximately six gate-delays per data item, which in its 0.35 micron technology is in excess of 1.2 Giga-Data-Items per second (GDI/s); the corresponding latency ... View full abstract»

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  • Squaring the FIFO in GasP

    Publication Year: 2001 , Page(s): 194 - 205
    Cited by:  Papers (19)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (640 KB) |  | HTML iconHTML  

    This paper presents a method for designing a special type of asynchronous circuits, called GasP circuits, and illustrates the method by a novel design of a low-latency, high-throughput FIFO, called a square FIFO. The design method includes a graphical notation that permits the specification not only of circuit topology but also of the time separation between any two succeeding events. A square FIF... View full abstract»

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  • Partial-order correctness-preserving properties of delay-insensitive circuits

    Publication Year: 2001 , Page(s): 74 - 83
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (724 KB) |  | HTML iconHTML  

    Delay-insensitive (DI) circuits are a class of asynchronous circuits that operate correctly regardless of delays in components or wires. We model such circuits using their traces, or sequences of events (signal transitions) that occur during the operation of the circuit. DI circuits can be characterized by certain properties regarding swapping consecutive events in traces. We focus on the exhausti... View full abstract»

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  • AMULET3i cache architecture

    Publication Year: 2001 , Page(s): 152 - 161
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (956 KB) |  | HTML iconHTML  

    This paper presents an evaluation of a range of cache features applied to an asynchronous, dual-ported copy-back cache. The design has been optimised for the AMULET3 asynchronous microprocessor core, but the techniques developed are much more widely applicable. It is shown that using a copy-back cache with a victim cache would gives a noticeable performance improvement on the existing fabrication ... View full abstract»

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  • Synchronous handshake circuits

    Publication Year: 2001 , Page(s): 86 - 95
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (764 KB) |  | HTML iconHTML  

    We present the synchronous implementation of handshake circuits as an extra feature in the otherwise asynchronous design flow based on Tangram. This synchronous option can be used in the mapping onto FPGAs or as a fallback option to provide a circuit that is easier to test and integrate in a synchronous environment. When single-rail and synchronous realizations of the same handshake circuit are co... View full abstract»

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  • How to achieve worst-case performance [self-timed circuit design]

    Publication Year: 2001 , Page(s): 206 - 216
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    “Average case performance” is an oft-cited motivation for self-timed design. In self-timed designs, computations proceed according to handshakes, and these handshakes can reflect the actual time required for operations rather than the worst-case time. The intuitive argument is that this should lead to systems whose performance reflects the average-cease performance of their components.... View full abstract»

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  • Designing an asynchronous bus interface

    Publication Year: 2001 , Page(s): 108 - 117
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    By presenting the design of an asynchronous bus interface for the 80C51 microcontroller we show that nonchannel communications are needed to come to a modular and efficient solution. We derive the bus design by applying five transformations to an initial design that is completely based on channel communications. In each of the steps we first discuss the problem to be solved. The final design uses ... View full abstract»

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  • A multi-radix approach to asynchronous division

    Publication Year: 2001 , Page(s): 25 - 34
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled data with data-dependent computation time. In this scheme the selection function is very simple and may be implemented using a fast adder This function speculates the result digit a... View full abstract»

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  • Asynchronous design and the pursuit of low power

    Publication Year: 2001
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (24 KB) |  | HTML iconHTML  

    Summary form only give, as follows. Two often cited arguments for the inherent low-power benefit of asynchronous or self-timed design is that the clock signals cause unnecessary switching activity and that the clock signals themselves dissipate a large portion of the total chip power. However, the careful and explicit application of conditional clocking and the use of novel clock driver circuits i... View full abstract»

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  • Performance evaluation of Cascade ALU architecture for asynchronous super-scalar processors

    Publication Year: 2001 , Page(s): 162 - 172
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (804 KB) |  | HTML iconHTML  

    Current out-of-order architectures have the critical path in the memory structure. Since the memory access delay mainly consists of wire delays, the feature size reduction will make little contribution to the critical path reduction. Therefore, the performance of the out-of-order architecture will not improve in spite of an expected advance in future technologies. To solve this problem, we present... View full abstract»

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  • Testing asynchronous circuits: help is on the way!

    Publication Year: 2001
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (44 KB)  

    Summary form only given. The author describes the synergies in test problems with synchronous designs that will help in the testing of asynchronous designs. In particular, he touches upon the ATE architectures and points out where the current architectures are inadequate in supporting the testing of asynchronous circuits. The author then describes the current and planned features in ATEs that will... View full abstract»

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  • Where are the async millionaires?

    Publication Year: 2001
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (44 KB)  

    Summary form only given. The author considers that too often, asynchronous (Async) methodologies are postulated to be a “possibly” better solution for various problems in the design of computers. He goes on to discuss the real current issues with general purpose computing, where Async methodologies will come in, what form he thinks it should take, and what the barriers are. The possibi... View full abstract»

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  • PCA-1: a fully asynchronous, self-reconfigurable LSI

    Publication Year: 2001 , Page(s): 54 - 61
    Cited by:  Papers (8)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    This paper describes the asynchronous device features of PCA-1, which is the first VLSI to realize the Plastic Cell Architecture (PCA). PCA is an autonomously reconfigurable hardware architecture consisting of a programmable logic layer and a network of built-in facilities. To realize run-time generation and the deletion of circuit objects with variable grain, the circuits on the logic layer are p... View full abstract»

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  • GasP: a minimal FIFO control

    Publication Year: 2001 , Page(s): 46 - 53
    Cited by:  Papers (86)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (580 KB) |  | HTML iconHTML  

    The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, for round-robin scatter and gather for data dependent scatter and gather and for join on demand through arbitration. The family is designed so that each stage operates at the speed of a three-inverter ring oscillator Test chips in 0.35 micron technology exhibit throughput in excess... View full abstract»

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  • An analysis of reshuffled handshaking expansions

    Publication Year: 2001 , Page(s): 96 - 105
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (708 KB) |  | HTML iconHTML  

    We present a method for reasoning about the synchronization behavior of reshuffled handshaking expansions. The technique introduced converts the handshaking expansion into communicating hardware processes. We identify and discuss some of the limitations of the method. We show how the approach can be applied to analyze both the performance and the correctness of handshaking expansions View full abstract»

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  • A practical comparison of asynchronous design styles

    Publication Year: 2001 , Page(s): 36 - 45
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (876 KB) |  | HTML iconHTML  

    It is well known that single-rail bundled-delay circuits provide good area efficiency but it can be difficult to match them with appropriate delay models. Conversely delay insensitive circuits such as those employing dual-rail codes are larger but it is easier to ensure timing correctness. In terms of speed bundled-delay circuits need conservative timing but dual-rail circuits can require an appre... View full abstract»

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  • Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

    Publication Year: 2001 , Page(s): 118 - 126
    Cited by:  Papers (33)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (644 KB) |  | HTML iconHTML  

    The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1... View full abstract»

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