Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001

29-30 Jan. 2001

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  • Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001

    Publication Year: 2001
    Request permission for reuse | PDF file iconPDF (138 KB)
    Freely Available from IEEE
  • The SawMill framework for virtual memory diversity

    Publication Year: 2001, Page(s):3 - 10
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (731 KB) | HTML iconHTML

    We present a framework that allows applications to build and customize VM services on the LA microkernel. While the LA microkernel's abstractions are quite powerful, using these abstractions effectively requires higher-level paradigms. We propose the dataspace paradigm which provides a modular VM framework. The modularity introduced by the dataspace paradigm facilitates implementation and permits ... View full abstract»

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  • Adaptive interfacing with reconfigurable computers

    Publication Year: 2001, Page(s):11 - 18
    Cited by:  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (748 KB) | HTML iconHTML

    A reconfigurable computer consists of reconfigurable logic circuits added to a conventional processor to give a computer where both the hardware and the software can be programmed on an application by application basis. Despite significant research, reconfigurable computers have failed to gain widespread acceptance as a high-speed computing replacement for conventional supercomputers. This paper d... View full abstract»

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  • Error detection for adaptive computing architectures in spacecraft applications

    Publication Year: 2001, Page(s):19 - 26
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (771 KB) | HTML iconHTML

    The Australian FedSat satellite will incorporate a payload to validate the use of adaptive computing architectures in spacecraft applications. The technology has many exciting benefits for deployment in spacecraft, but the space environment also represents unique challenges which must be addressed. An important consideration is that modern SRAM Field Programmable Gate Arrays (FPGAs), such as the X... View full abstract»

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  • Components + security = OS extensibility

    Publication Year: 2001, Page(s):27 - 34
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (954 KB) | HTML iconHTML

    Component-based programming systems have shown themselves to be a natural way of constructing extensible software. Well-defined interfaces, encapsulation, late binding and polymorphism promote extensibility, yet despite this synergy, components have not been widely employed at the systems level. This is primarily due to the failure of existing component technologies to provide the protection and p... View full abstract»

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  • Application domains for fixed-length block structured architectures

    Publication Year: 2001, Page(s):35 - 44
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1130 KB) | HTML iconHTML

    In order to tackle the growing complexity and interconnects problem in modern microprocessor architectures, computer architects have come up with new architectural paradigms. A fixed-length block structured architecture (BSA) is one of these paradigms. The basic idea of a BSA is to generate blocks of instructions, called BSA-blocks, statically (by the compiler) and executing these blocks on a dece... View full abstract»

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  • A simulator for high speed digital communications

    Publication Year: 2001, Page(s):45 - 54
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (807 KB) | HTML iconHTML

    Since parallel processors are generally constrained by the available interprocessor data transfer capability, system designers generally try to push interconnection systems to their limits in bandwidth. Practical and economic systems are constrained by many physical and packaging considerations such as a need to use commercially available connectors. We describe here VisiSolve-a simulator that we ... View full abstract»

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  • Stacking them up: a comparison of virtual machines

    Publication Year: 2001, Page(s):55 - 61
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (671 KB) | HTML iconHTML

    A popular trend in current software technology is to gain program portability by compiling programs to an intermediate form based on an abstract machine definition. Such approaches date back at least to the 1970s, but have achieved new impetus based on the current popularity of the programming language Java. Implementations of language Java compile programs to bytecodes understood by the Java Virt... View full abstract»

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  • DStride: data-cache miss-address-based stride prefetching scheme for multimedia processors

    Publication Year: 2001, Page(s):62 - 70
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (875 KB) | HTML iconHTML

    Prefetching reduces cache miss latency by moving data up in memory hierarchy before they are actually needed. Recent hardware-based stride prefetching techniques mostly rely on the processor pipeline information (e.g. program counter and branch prediction table) for prediction. Continuing developments in processor microarchitecture drastically change core pipeline design and require that existing ... View full abstract»

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  • Two cache lines prediction for a wide-issue micro-architecture

    Publication Year: 2001, Page(s):71 - 79
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1149 KB) | HTML iconHTML

    Modern micro-architectures employ superscalar techniques to enhance system performance. The superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. In this paper, we propose the Grouped Branch Prediction (GBP) that can recognize and predict multiple branches in the same instruction cache line for a wid... View full abstract»

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  • Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines

    Publication Year: 2001, Page(s):80 - 88
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (824 KB) | HTML iconHTML

    This paper looks at a combination of two techniques, one of which, using a vector instruction set, has a long history dating back to pipelined vector supercomputers, such as the Cray 1 and its successors. The other technique, multi-threading, is also well understood. The novel approach proposed in this paper combines both vertical and horizontal micro-threading with vector instruction descriptors.... View full abstract»

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  • High-performance extendable instruction set computing

    Publication Year: 2001, Page(s):89 - 94
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (582 KB) | HTML iconHTML

    In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset and immediate operands can be extended to 32 bits via the operation of... View full abstract»

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  • Fault-tolerant routing on Complete Josephus Cubes

    Publication Year: 2001, Page(s):95 - 104
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (644 KB) | HTML iconHTML

    This paper introduces the Complete Josephus Cube, a fault-tolerant class of the recently proposed Josephus Cube and proposes a cost-effective, fault-tolerant routing strategy for the Complete Josephus Cube. For a Complete Josephus Cube of order r, the routing algorithm can tolerate up to (r+1) encountered component faults in its message path and generates routes that are both deadlock-free and liv... View full abstract»

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  • Password-capabilities: their evolution from the password-capability system into Walnut and beyond

    Publication Year: 2001, Page(s):105 - 113
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (970 KB) | HTML iconHTML

    Since we first devised and defined password capabilities as a new technique for building capability-based operating systems, a number of research systems around the world have used them as the bases for a variety of operating systems. Our original Password-Capability System was implemented on custom built hardware with a novel address translation and protection scheme specifically designed to supp... View full abstract»

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  • Retargetable cache simulation using high level processor models

    Publication Year: 2001, Page(s):114 - 121
    Cited by:  Patents (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (625 KB) | HTML iconHTML

    During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the Sim-nML processor description language. The retargetability helps in cache simulation and evaluation much before the ac... View full abstract»

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  • Exploiting Java instruction/thread level parallelism with horizontal multithreading

    Publication Year: 2001, Page(s):122 - 129
    Cited by:  Papers (5)  |  Patents (14)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (747 KB) | HTML iconHTML

    Java bytecodes can be executed with the following three methods: a Java interpreter running on a particular machine interprets bytecodes; a Just-in-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the machine executes the translated codes; and a Java processor executes bytecodes directly. The first two methods require no special hardware support for t... View full abstract»

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  • The first real operating system for reconfigurable computers

    Publication Year: 2001, Page(s):130 - 137
    Cited by:  Papers (16)  |  Patents (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (853 KB) | HTML iconHTML

    Traditional reconfigurable computing platforms are designed to be single user and have been acknowledged to be difficult to design applications for. The design tools are still primitive and as reconfigurable computing becomes mainstream the development of new design tools and run time environments is essential. As the number of system gates is reaching 10 million on current FPGAs, there is an incr... View full abstract»

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  • Performance evaluation of a partial retraining scheme for defective multi-layer neural networks

    Publication Year: 2001, Page(s):138 - 145
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (685 KB) | HTML iconHTML

    This paper addresses an efficient stuck-defect compensation scheme for multi-layer artificial neural networks implemented in hardware devices. To compensate for stuck defects, we have proposed a two-stage partial retraining scheme that adjusts weights belonging to a neuron affected by defects based on back-propagation (BP) algorithm between two layers. For input neurons, the partial retraining sch... View full abstract»

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  • Author index

    Publication Year: 2001, Page(s): 147
    Request permission for reuse | PDF file iconPDF (37 KB)
    Freely Available from IEEE