2015 IEEE 24th North Atlantic Test Workshop

11-13 May 2015

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  • [Front cover]

    Publication Year: 2015, Page(s): C4
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  • [Title page i]

    Publication Year: 2015, Page(s): i
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  • [Title page iii]

    Publication Year: 2015, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2015, Page(s): iv
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  • Table of contents

    Publication Year: 2015, Page(s):v - vi
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  • Welcome Message

    Publication Year: 2015, Page(s): vii
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  • Conference Organization

    Publication Year: 2015, Page(s): viii
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  • Reviewers

    Publication Year: 2015, Page(s): ix
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  • Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

    Publication Year: 2015, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB) | HTML iconHTML

    Machine learning techniques based on Data Miningare employed for automatic assertion generation in hardwaredigital design verification. This paper presents a new miningtechnique to extract all design properties from simulation traces.The extracted properties cover all possible design assertionseither at system level or Register Transfer Logic (RTL)verification depending on the simulated design lev... View full abstract»

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  • Clock Domain Imbalances and Their Impact on Test Architecture

    Publication Year: 2015, Page(s):7 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    Clock architecture in digital designs goes through an iterative cycle of timing analysis, routing and placement and fixes to meet timing. At a higher level, each of these steps must be done in different scenarios for example: test mode and functional mode. There can be multiple test modes also. There can be many functional clocks in the design adding to the complexity. Each functional clock can sp... View full abstract»

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  • Hybrid Hierarchical and Modular Tests for SoC Designs

    Publication Year: 2015, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (422 KB) | HTML iconHTML

    Modular test and hierarchical test of core-based System-on-Chip (SoC) are two widely used SoC test methodologies. In this paper, the hybrid test methodology that incorporates these two together is studied by using an industrial real case. Thorough experimental results are demonstrated to compare various scenarios of the hybrid hierarchical and modular tests for SoC designs. Based on the experiment... View full abstract»

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  • Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug

    Publication Year: 2015, Page(s):17 - 22
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (647 KB) | HTML iconHTML

    Since integrating memory blocks on-chip becameaffordable, embedded logic analysis has been employed duringpost-silicon validation and debugging. Failing traces obtainedthrough embedded logic analysis can be used to understand functionaldesign errors, a problem that has been studied extensivelyover the past decade. In this paper, we show that post-processingfailing traces using a computational appr... View full abstract»

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  • Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics

    Publication Year: 2015, Page(s):23 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1114 KB) | HTML iconHTML

    Self-reliance capabilities of mission-critical systems gain importance as technology scaling and logic capacity of SRAM-based reconfigurable devices increase. The Sustainable Modular Adaptive Redundancy Technique (SMART) is evaluated to optimize the reliability, availability, and energy efficiency of reconfigurable logic devices with a given area footprint. A Monte Carlo driven Continuous Markov T... View full abstract»

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  • An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices

    Publication Year: 2015, Page(s):33 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    Testing of every manufactured chip is an essential and crucial step in the semiconductor manufacturing process. It helps to ensure that customers get working chips that meet all the specifications. This is necessary to avoid the consequences and penalties that are incurred if a faulty chip is found by the customers. The current trend in the semiconductor industry is to attempt to increase the comp... View full abstract»

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  • At-Speed Path Delay Test

    Publication Year: 2015, Page(s):39 - 42
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB) | HTML iconHTML

    This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by a... View full abstract»

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  • A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures

    Publication Year: 2015, Page(s):43 - 48
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (454 KB) | HTML iconHTML

    This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM ... View full abstract»

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  • Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

    Publication Year: 2015, Page(s):49 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1327 KB) | HTML iconHTML

    With the reduced-pin-count test (RPCT) being adopted for multi-core systems-on-chip (SoCs) that usually support test compression as well, test speed is reduced due to the narrower input bandwidth. In this work, we propose an idea to combine multi-valued logic (MVL) test application with RPCT technology, which increases the data rate of test channels to avoid compromising test speed for the interfa... View full abstract»

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  • SoC TAM Design to Minimize Test Application Time

    Publication Year: 2015, Page(s):55 - 60
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB) | HTML iconHTML

    We propose a new test access mechanism(TAM) design to reduce the System-on-chip (SoC) test application time (TAT) under various hardware and power constraints. Prior works on TAM design focus on designing TAM architecture based on fixed cores parameters, which assumes unchanged internal scan chains and layout arrangement of cores, and therefore is unable to make effective use of SoC resources for ... View full abstract»

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  • Author index

    Publication Year: 2015, Page(s): 61
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  • [Publisher's information]

    Publication Year: 2015, Page(s): 62
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