2015 Ninth International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip

19-19 Jan. 2015

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  • [Front cover]

    Publication Year: 2015, Page(s): C4
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  • [Title page i]

    Publication Year: 2015, Page(s): i
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  • [Title page iii]

    Publication Year: 2015, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2015, Page(s): iv
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  • Table of contents

    Publication Year: 2015, Page(s): v
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  • Introduction

    Publication Year: 2015, Page(s): vi
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  • Workshop Organizers

    Publication Year: 2015, Page(s): vii
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  • Technical Program Committee

    Publication Year: 2015, Page(s): viii
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  • Towards High-Performance and Power-Efficient Optical NoCs Using Silicon-in-Silica Photonic Components

    Publication Year: 2015, Page(s):1 - 4
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    Networks-on-Chips (NoCs) are meeting the growing inter-tile communication needs of multicore chips. However, achieving system scalability by utilizing hundreds of cores on-chip requires high performance, yet energy-efficient on-chip interconnects. As electrical interconnects are marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high thr... View full abstract»

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  • Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems

    Publication Year: 2015, Page(s):5 - 8
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    The fundamental choice to be taken when sharing an optical ring between multiple communication actors is whether to avoid contention from the ground up by means of non-interfering concurrent transmissions on different wavelengths, or by resolving it at runtime through arbitration mechanisms.This paper aims at assessing power efficiency of Wavelength-Selective vs. Wavelength-Arbitrated routing meth... View full abstract»

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  • Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip

    Publication Year: 2015, Page(s):9 - 12
    Cited by:  Papers (9)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (213 KB) | HTML iconHTML

    Next to performance, it becomes increasingly important that Networks-on-Chip (NoCs) also provide security features such as access control, authentication and availability. They are usually implemented by firewalls at the network interfaces (NIs) of the processing elements (PEs). This paper provides a more efficient way to integrate these security requirements into application-specific NoCs by inse... View full abstract»

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  • A Parallel Gauss-Seidel Algorithm on a 3D Torus Network-on-Chip Architecture

    Publication Year: 2015, Page(s):13 - 16
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    We propose an efficient parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus network-on-chip (NoC) architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under t... View full abstract»

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  • A Co-design Approach for Hardware Optimizations in Multicore Architectures Using MCAPI

    Publication Year: 2015, Page(s):17 - 20
    Cited by:  Papers (1)
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    Current SoC platforms targeting high-performance with high power efficiency rely on replicating several processing cores while adding dedicated hardware units for specific tasks. However, programming such architectures demand a high effort when compared to homogeneous multiprocessors since there is no widely used standard for heterogeneous embedded systems. The use of standard application programm... View full abstract»

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  • Author index

    Publication Year: 2015, Page(s): 21
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  • [Publisher's information]

    Publication Year: 2015, Page(s): 22
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