2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing

19-21 Jan. 2015

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  • [Front cover]

    Publication Year: 2015, Page(s): C4
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  • [Title page i]

    Publication Year: 2015, Page(s): i
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  • [Title page iii]

    Publication Year: 2015, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2015, Page(s): iv
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  • Table of contents

    Publication Year: 2015, Page(s): v
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  • Message from General Chairs

    Publication Year: 2015, Page(s): vi
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  • Message from Program Chairs

    Publication Year: 2015, Page(s):vii - viii
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  • Conference Organization

    Publication Year: 2015, Page(s): ix
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  • Program Committee

    Publication Year: 2015, Page(s): x
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  • Invited talks

    Publication Year: 2015, Page(s):xi - xiii
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (42 KB)

    Provides an abstract for each of the invited presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

    Publication Year: 2015, Page(s):1 - 8
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (2908 KB) | HTML iconHTML

    We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next to the CPU die. The cache interconnection system is realized through WDM optical interfaces that connect the shared cache module with the processing cores and the Main Memory via... View full abstract»

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  • On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs

    Publication Year: 2015, Page(s):9 - 16
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    Future many-core systems will require energy-efficient, high-throughput and low-latency communication architectures. Silicon Photonics appears today as a promising solution to achieve these goals. However, the photonics inability to perform inflight buffering and logic suggests the use of Hybrid Photonic-Electronic architectures. In order to exploit the full potential of photonics, it is essential... View full abstract»

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  • Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization

    Publication Year: 2015, Page(s):17 - 24
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1405 KB) | HTML iconHTML

    Many researchers are currently at work to assess the congruent multiples in performance and energy efficiency that should be expected by the photonic integration of multi and many-core processors. However, such processors and their interconnection networks are typically viewed as monolithic resources, which fails to capture the most recent trends in the usage model of these computation-rich device... View full abstract»

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  • Optimal Power Efficient Photonic SWMR Buses

    Publication Year: 2015, Page(s):25 - 32
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (803 KB) | HTML iconHTML

    In this paper we solve the problem of minimizingthe power consumption in SWMR (single writer, multi reader)optical buses for both the ring and tree based configurations. Tominimize the power consumption it is necessary to design thebeam splitters in a SWMR bus optimally. A prior approach byBinzhang et al. [5] proposes to use an exponential time NLPbased solution for solving a related problem, and ... View full abstract»

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  • Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip

    Publication Year: 2015, Page(s):33 - 39
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (661 KB) | HTML iconHTML

    The current evolution of system architectures leads towards implementation of large number of processor cores into the same circuit. This evolution actually supports the performance increase and provides the capability to support the execution of very complex applications. Nevertheless, if these new architectures propose high computational performances, an important bottleneck appears for the comm... View full abstract»

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  • Author index

    Publication Year: 2015, Page(s): 40
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  • [Publisher's information]

    Publication Year: 2015, Page(s): 42
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