By Topic

Advanced Packaging Materials: Processes, Properties andInterfaces, 2000. Proceedings. International Symposium on

Date 6-8 Aug. 2000

Filter Results

Displaying Results 1 - 25 of 64
  • Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.00TH8507)

    Publication Year: 2000
    Save to Project icon | Request Permissions | PDF file iconPDF (348 KB)  
    Freely Available from IEEE
  • Hygroscopic behavior and in-line thermo-mechanical treatment of polymeric material effects on PBGA warpage

    Publication Year: 2000 , Page(s): 243 - 248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (555 KB)  

    The interaction of hygroscopic behavior and thermo-mechanical treatment of polymeric material is highly interesting, not only from the warpage and coplanarity point of view but also from the in-plane deformation characteristics. Since the moisture absorption of substrates has been classified as one of the indicators to qualify package materials, in this study, package warpage relating the substrate quality and package process flow was addressed. The package size effect on package warpage and coplanarity was examined The hygroscopic behavior of plastic packages on warpage was investigated by two different storage patterns such as dry packing and on-floor exposure. Moreover, the in-line thermo-mechanical treatment (clamping) effect on warpage vs. hygroscopic behavior was discussed. Finally, from Moire interferometry, the fringe patterns of specimens with and without clamping and before and after soaking were compared. It is shown that clamping is able to control the warpage successfully. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Index of authors

    Publication Year: 2000 , Page(s): 349
    Save to Project icon | Request Permissions | PDF file iconPDF (86 KB)  
    Freely Available from IEEE
  • Materials options for dielectrics in integrated capacitors

    Publication Year: 2000 , Page(s): 38 - 43
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Value requirements for capacitors in modern microelectronic assemblies extend over six orders of magnitude from about 1 pF to 1 μF. For many applications this entire range must be present on the same substrate with the lower end providing a variety of filtering, timing, RF and A/D purposes and the upper end serving decoupling and other energy-storage functions. The smaller capacitors generally require stricter tolerances and tighter stabilities than the larger units. There are many candidate dielectric materials, deposition/etching processes and plate configurations for integrating these devices. It is difficult, if not impossible, for any single dielectric material and capacitor configuration to provide this entire range without either the highest or lowest-valued components occupying too large an area, exhibiting excessively high series resistance, or being too small to fabricate with acceptable tolerance. Therefore, it will often be necessary to mix integrated capacitor technologies on a single substrate. BCB, polyimide and SiO2 provide a small enough capacitance and sufficient tolerance for the bottom end of the range while anodized metals or ferroelectric powders in epoxy thin films can cover decoupling termination and some energy storage into the range of hundreds of nF. Ferroelectric thin films provide much higher dielectric constants but are currently difficult to integrate, especially for small values, and have less temperature, frequency and bias stability than paraelectrics. Once it becomes possible to form ferroelectric thin films at temperatures low enough for organic substrates these films will be very useful for energy storage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Alternate solder bump technologies for flip chip applications

    Publication Year: 2000 , Page(s): 124 - 130
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    Flip chip on board technology using eutectic Sn-Pb solder bumps to reduce cost associated with cladded printed circuit board is becoming more common in the industry. However, the, low melting eutectic Sn-Pb bumps are subjected to issues such as solder extrusion during subsequent reflow processes and solder microstructure coarsening after extensive high temperature exposures such as the under-the-hood automotive environment. To address these issues, we have developed a stencil print solder bumping process that is applicable to various alternatives to eutectic Sn63Pb37 solder bump. The process has been demonstrated to solder alloys with melting range between 211°C and 265°C. Many alloys of such melting range have potential to meet temperature hierarchy requirement for flip chip BGA packages. Additionally, some high temperature solders contain no lead, which is good for environment and for reducing soft error rate of memory IC's. This paper summarized the alternate solder bump technology development, which uses the print solder bump process, the most flexible method to deposit the many bump metallurgies. Solder paste material down selection, process development, bump characterization, and flip chip interconnect reliability results for various alloy bumps are reported. Typical bump height uniformity is 135±3.5 μm, which is equivalent of 3% of bump height standard deviation. In many cases, bump composition is close to the theoretical eutectic composition of selected alloy systems. Preliminary reliability evaluation of direct chip attach packages having high m.p. bumps under-65°C/+150°C air-to-air temperature cycle test are reported View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of new reworkable epoxy resins for flip chip underfill applications

    Publication Year: 2000 , Page(s): 289 - 294
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    Underfill is a polymeric material used in the flip-chip devices that fills the gap between an IC chip and an organic board, and encapsulates the solder interconnects. This underfill material can dramatically enhance the reliability of the flip-chip devices as compared to non-underfilled devices. Current employed underfills are mainly silica filled epoxy-based materials that are not reworkable after curing, an obstacle in Flip-Chip on Board (FCOB) and Multi-chip Module (MCM) technology developments where unknown bad dies is still a concern. Reworkable underfill is the key material to address the non-reworkability of the FCOB packages. We have synthesized a series of thermally degradable epoxies that show good reworkability. However, all these epoxies have degradation temperature higher than 250°C. Besides, they are cycloaliphatic-only-based which have shown weakness in toughness and thus may not perform well for very high reliability applications. In the search for high performance epoxy resins for reworkable underfills, our approach is to incorporate aromatic moiety and thermally labile group that decomposes around solder reflow temperature. This paper reports part of our recent approach in the study and development of new epoxy resins that may offer better rework properties. Two new diepoxides containing tertiary ester, tertiary carbonate, and aromatic moieties were synthesized. These epoxy compounds exist as liquids at ambient temperature. The curing properties of these two epoxides and thermal properties of cured resins of these epoxy compounds were characterized with DSC, TGA and TMA View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of the environmental protection of photo BCB polymers (CycloteneTM 4000)

    Publication Year: 2000 , Page(s): 90 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    With the demand for higher interconnect density increasing, the ability of polymeric insulation to resist current flow and protect circuits from corrosion is becoming more and more important. BCB polymer is being used commercially on many high density devices which must function in non-hermetic environments. It was therefore of interest to quantify the change in resistance and leakage current (under temp-humidity-bias), of BCB encapsulated circuits by conducting surface insulation resistance (SIR) and triple track testing (TTT). SIR of all the Cyclotene samples ranged from 7.5×108 to 8.8×109 Ω. TTT reveals stable resistance of all samples past 500 hours. Leakage current measurements of ⩽4×10 -11 amperes were observed. The BCB samples show results equal to or better than the Dow Corning vulcanized rubber control, indicating excellent circuit protection capability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wafer level package using double balls

    Publication Year: 2000 , Page(s): 198 - 200
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    The highest potential for future single chip packages has the wafer level approach: the package is completed directly on the wafer, then singulated by dicing for assembly in a flip chip fashion. The technological structure of this double-ball CSP is a pad redistributed die with a solder ball array a stress compensation layer (SCL) embedding the solder balls before a second set of solder balls is stencil printed or placed on top of the embedded balls. The reliability of the wafer-level CSP presented here was evaluated. The test chip was a 1 cm×1 cm square chip which was redistributed to an 14×14 ball array with a pitch of 0.5 mm. JEDEC level 3, 1000 cycles AATC (-55°C/+125°C) and 48 h autoclave on component level were passed. On board level 1000 hours humidify storage at 85°C (85/85 test) was passed and only 20% of the WL-CSPs had opens after 1000 cycles -55/+125°C View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Halogen-free materials for PWB and advanced package substrate

    Publication Year: 2000 , Page(s): 221 - 226
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    We have developed halogen-free technologies, consisting of resin systems with high filler content. The point of the technology is the development of a new resin system (RO resin) which incorporates nitrogen into the molecule frame in large quantities. The high filler content technology develops a new filler interphase control system (FICS) which enables the high dispersion of fillers. A variety of halogen-free substrates which can be applied to diversified needs have been developed by combining these technologies. They are MCL-RO-67G, a thin laminate for the multi-layer PWBs, MCF-4000G, a build-up material for high density interconnect (HDI), and MCL-E-679F(G), a high Tg laminate for advanced plastic IC packages (PKGs) and PWBs. These materials have excellent heat-resistance, and are suitable for lead-free solder. The robustness towards temperature, humidity and frequency of those materials is better than that of current materials. The synthetic board design of environmental harmony type becomes easy by combined use of these materials View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reworkable no-flow underfills for flip chip applications

    Publication Year: 2000 , Page(s): 165 - 171
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    Underfill is a polymeric material used in the flip-chip devices that fills the gap of IC chip and organic board, and encapsulates the solder interconnects. This underfill material can dramatically enhance the reliability of the flip-chip devices as compared to the non-underfilled devices. No-flow underfill is a new type of underfill that allows simultaneous solder bump reflow and underfill cure, which leads to more efficient no-flow underfilling process as compared to standard underfilling process. Reworkable underfill is another type of underfill that allows the faulty chip to be replaced individually. It is the key material to address the non-reworkability issue of current underfills. Both underfills are very important to the continuous advancement of flip chip technology. The combination of these two good features in one underfill is a novel idea. However, currently no such kind of research is carried out. Our goal is to develop reworkable no-flow underfill, an underfill that not only can be used in no-flow underfilling process but also makes the flip-chip device reworkable. We are taking two approaches for this new type of underfill. The first one is to add special additive into a no-flow underfill formulation to make it reworkable. The second approach is to develop no-flow underfill based on a new epoxy resin that decomposes around 260°C. Two underfills are developed based on these approaches. Comparing to the standard no-flow underfill, these two had similar properties including curing and fluxing, but they showed reworkability while the standard no-flow underfill was not reworkable View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formation of Ni3Sn4 at the boundary between Sn-Pb soldering layers and Au/Ni plated coatings

    Publication Year: 2000 , Page(s): 135 - 140
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    Ni3Sn4 formation should affect the reliability of soldering between package and printed circuit board. We have investigated the formation of the Ni3Sn4 at the boundary between Sn-Pb soldering layers and electro-, or electroless plated Au/Ni coatings. In the case of Sn-Pb solders, the shapes of Ni3Sn4 intermetallic compounds (IMC), which was formed at the boundary between the solder and Ni plated coatings, were shown to have many differences between them. We discovered that the shape of Ni3Sn4 would be controlled by p content of Ni-P plated coatings, the Pb content in the soldering layers, and the thickness of immersion Au plated coatings. Under the specific conditions, the shape of Ni3Sn4 using the electroless Au/Ni plating would become to be similar to the electroplated Au/Ni, then the reliability of solder joint could be higher View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Materials and process technology: materials [flip chip assembly]

    Publication Year: 2000 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A new assembly process for flip chip assembly has been demonstrated to be feasible for manufacturing. The use of heated thermodes on the bonding heads of the flip chip bonder allows the underfill encapsulant, whether film or paste, to be rapidly cured. This eliminates the need for underfill after bump attach and improves the reliability of the flip chip assembly. The NCF and NCP processes also offer the industry an assembly method for achieving high throughput flip chip attach at lower manufacturing costs. This new assembly process couples electrically conductive polymer bumps with a new generation of polymeric encapsulants that can be applied before bumping View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ultra CSPTM Bump on Polymer structure

    Publication Year: 2000 , Page(s): 211 - 215
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    The wafer level Ultra CSP has the potential for DRAM and Direct RambusTM DRAM (D-RDRAMTM) applications for three reasons: excellent electrical performance, sufficient design margin, and low cost. To meet the desired capacitance requirements, a design concept called Bump-on-Polymer (BOP) structure was developed at Flip Chip Technologies. Three test vehicles were defined for this study. The first test vehicle is a 0.80 mm pitch 90 I/O daisy chain device to emulate a DRAM device. The second test vehicle has the same foot-print as a D-RDRAM (128/144) with 0.8 mm pitch in the x-direction and 1.0 mm pitch in the y-direction. The third test vehicle is a generic 0.50 mm pitch daisy chain device which can be bumped in 6×6, 8×8, and 10×10 array for DNP study. This paper reviews the board level thermal cycle test results on the BOP structure of these test vehicles in terms of package configuration, substrate design, solder ball size, and DNP effect. Issues in wafer level processes and reliability test conditions were also addressed. Recommendations are provided for the implementation of Ultra CSP for DRAM applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel conductive adhesives with stable conductivity and high impact resistance

    Publication Year: 2000 , Page(s): 18 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    Surface Mount Conductive Adhesives (SMCAs) provide an environmentally friendly solution for interconnections in electronic applications. In addition, SMCAs offer other attractive technical advantages over conventional Sn/Pb metal solders including low temperature processing and fine pitch capability. Two shortcomings of current commercial SMCA products are unstable electrical conductivity (contact resistance), under elevated temperature and humidity conditions, and inferior impact resistance of the adhesive interconnections. Systematic studies in the past have identified the fundamental mechanisms contributing to unstable contact resistance and poor impact strength of these SMCA materials. This paper will compare and contrast mechanical and electrical properties of several novel SMCAs that were developed utilizing two distinctly different material science approaches View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel single pass reflow encapsulant for flip chip application

    Publication Year: 2000 , Page(s): 97 - 101
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    A series of novel single pass reflow encapsulants with varied Tg's below 125°C were investigated under multiple testing methods. The single pass reflow encapsulant with the lowest Tg (65°C) showed some of the best reliability, passing over 1000 cycles of LLTC (-55° to 125°C) testing. These results indicate that the Tg and CTE of the encapsulant are important but not critical parameters to the reliability of the flip chip package with single pass reflow encapsulants View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Material challenges for wafer level packaging

    Publication Year: 2000 , Page(s): 68 - 73
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    Flip chip as the smallest packaging design has been used in more and more electronic applications. Flip chip underfill is an essential component for the reliability of the package. Currently, the dispensing process is done on each individual chip level after the solder interconnects have been made. The device then has to go through a separate curing process to harden the underfill material. The current underfilling process is cumbersome and is one of the cost drivers of flip chip application. In wafer level flip chip packaging, the dispensing is made over the whole wafer in one step. After dicing, the reflow and the curing of underfill will be accomplished also in one step. The saving on process cost will be substantial. The new process brings new challenges to underfill material development. In addition to performing the reinforcement role as an underfill, these new materials have to be compatible with the proposed wafer level process. In addition, the underfill material has to act as a fluxing agent during solder reflow. The underfill materials also have to demonstrate good room temperature stability after being dispensed onto wafer, handled at ambient environment, and before being cured in the reflow oven. The authors will discuss the parameters that determine the material performance at each processing step as well as the material development effort in a wafer-level underfill development program, which is sponsored by the Advanced Technology Program (ATP) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of thermal ageing on the shear strength of lead-free solder joints

    Publication Year: 2000 , Page(s): 152 - 157
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    As a response to the proposed legislation and regulations restricting the use of lead-based solders in the electronics industry, efforts to develop alternative solders have increased dramatically. In this work lead-free solder alloys with compositions of Sn96.5-Ag3.5, Sn96.3-Ag3.2-Cu0.5, Sn93.5-Ag3.5-Bi3 and Sn90-Ag2-Bi7.5-Cu0.5 (wt%) have been used to solder copper “components” to Ni/Au and Sn/Pb metallisations in order to simulate the solder joint in electronics. The shear strength of the soldered joints after thermal ageing at 25°C, 100°C and 150°C for 200 hours, 500 hours and 1000 hours have been evaluated. The fracture surfaces have been studied using scanning electron microscopy with energy dispersive spectroscopy. In general the shear strength decreases as the ageing time increases, however the Sn-Ag systems are shown to be more stable with ageing temperature and time. Bismuth containing alloys are shown to have the highest strength initially but after ageing the strength of the joints become very weak View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Next generation ALIVH substrate for bare chip direct mounting

    Publication Year: 2000 , Page(s): 227 - 232
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    The next generation ALIVH(R) substrate named ALIVH(R)-FB substrate was developed. The ALIVH-FB substrate has a structure that fine layers were formed on the surface of the conventional ALIVH substrate. The design rule of the core layer is Line/Space (LIS)=50/50 μm, Via hole diameter/Land diameter (V/L)=120/250 μm and the rule of fine layer is L/S=25/25 μm, V/L=50/150 μm. Three technologies are developed: thin insulator layer by the film material with high heat resistance; fine via hole drilling process by the YAG THG laser and fine interconnection technology using conductive copper paste; and fine layer fabrication by the transfer process. The technologies display the following features: high wiring density by the Fine Via on Via structure; film insulator with high heat resistance and low CTE for a high reliability joint between the bare chip and the substrate; good impedance control for the high frequency circuit; and a flat surface and high heat resistance for the bare chip mounting. The ALIVH-FB substrate is very suitable for the high pin count bare chip direct mounting View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 18th Annual Conference on Computer Documentation. ipcc sigdoc 2000. Technology and Teamwork. Proceedings. IEEE Professional Communication Society International Professional Communication Conference and ACM Special Interest Group on Documentation Conference (Cat. No.00CH37136)

    Publication Year: 2000
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    The following topics were dealt with: teamwork; system prototyping; technical communication education; distance teaching; user advocates; online document editing; Internet and Web design; globalization; professional communication and learning; process integration; process management; testing; online-based instruction; design collaboration; wordcraft; literate programming; documentation tools; and information migration View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of conductive adhesives filled with low-melting-point alloy fillers

    Publication Year: 2000 , Page(s): 7 - 13
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    Conventional isotropic conductive adhesives (ICAs) are composed of a polymeric matrix with silver flakes. As an alternative to lead-bearing solder, ICAs offer a number of benefits, but limitations do exist for ICA technology. ICAs filled with silver flakes generally show higher initial contact resistance, unstable contact resistance, and inferior impact strength. In this study, a new class of isotropic conductive adhesives was developed by using two different fillers, a silver flake and a low melting point alloy filler, in the ICA formulations. After curing, the metallurgical connection between the silver particles and between the silver particles and the nickel (Ni) substrate was observed using scanning electron microscopy (SEM). Initial contact resistance and contact resistance shift during elevated temperature and humidity aging of the formulated ICAs on a non-noble metal (nickel) were investigated and compared to those of ICA filled only with the silver flake. It was found that (a) the low-melting-point alloy filler could wet the Ag flakes and nickel (Ni) substrate very well and formed metallurgical connections; and (b) this ICA showed especially low initial contact resistance and stable contact resistance during aging on nickel metal compared to the ICA filled only with silver flakes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Investigation on effect of carbon black and polymer matrix on conductive polymer composites with positive temperature coefficient

    Publication Year: 2000 , Page(s): 343 - 348
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    It was found that the base resistivity of conductive polymer composite and its behavior of positive temperature coefficient (PTC) versus temperature depend on the filler carbon black. Carbon blacks with large particle size, small surface area, and small amount of aggregate structure lead to high base resistivity and large amplitude of PTC (defined as the ratio of maximum resistivity to the resistivity at room temperature). While, carbon blacks with small particle size, large surface area, and large amount of aggregate structure lead to low base resistivity and low PTC amplitude. In this paper, the base resistivity of polymer composite filled with bimodal carbon blacks (with both large and small carbon black particles) is reported. Effect of carbon black filler on crystallinity of polymer matrix will also be determined. The effect of polymer matrix on base resistivity and PTC amplitude will be demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Flipchip on board (FCOB): solderability, reliability and the role of surface finish

    Publication Year: 2000 , Page(s): 172 - 174
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    Five surface finishes were evaluated for their effects on the solderability and reliability of FCOB assembly. Several test vehicles were employed in this evaluation for different purposes. Test vehicle boards were pre-conditioned and processed to simulate the storage and actual production environment. The surface finishes were found to have profound impact on the solderability and reliability of flip chip on board. The interactions between surface finish, flip chip bump metallurgy and configuration, underfill material, flux and pad geometry must be taken into consideration and optimized to achieve both solderability and reliability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliability investigations of FCOB assemblies with process-induced defects

    Publication Year: 2000 , Page(s): 50 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1204 KB)  

    To develop comprehensive design guidelines, models and experiments cannot overlook process-induced imperfections in the FCOB assemblies. The following items were noted as being significant factors which were used for modeling and by thermal cycling tests: (a) varying stand-off-heights and alternative bump sizes, (b) underfill-particle settling, (c) underfill “delamination/void” effects, (d) underfill-to-bump coverage, (e) asymmetrical fillets vs. symmetrical fillets. A detailed numerical and experimental reliability study of perfect and imperfect flip chip assemblies has been completed. Experimental studies of the failure modes and of the mean cycles to failure are in good agreement with the failure modes and life time, as predicted by FEM for the different technological variants. A hierarchy of influences was worked out in three levels (important, medium, negligible). Most important imperfections resulting in a strong reliability decrease are particle settling, asymmetrical fillets and small and big voids View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Formation, distribution and failure effects of voids in vapor-phase soldered small solder volumes

    Publication Year: 2000 , Page(s): 141 - 144
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    The formation of voids in small solder volumes, e.g. flip-chip-soldered electronic components, is of vital interest to determine their reliability. The aim of the study was to understand the physical and chemical reasons for void formation in small solder volumes, the determination of void diameters depending on soldering temperature and flux content. A further investigation was made to define the strength of the solder balls depending on void diameter and void distribution. The diameter and the location of the voids was measured by X-ray-detection. The results show an increase of voids with increasing soldering time at constant temperature and a rapid decrease of void diameter at a soldering time nearby 60 sec followed by a slower increase of voids. The distribution of void diameter shows a great amount of small voids and only some big voids. The distribution of the void diameter is a skew distribution. The shear strength of the soldered joints shows only a little influence on the voids amount. These results give hints for the optimized time-temperature-curves for the best soldering profile. Further investigations are necessary to determine the influence of the voids to thermomechanical stresses and vibration behavior View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterization of underfill/passivation interfaces using fracture mechanics

    Publication Year: 2000 , Page(s): 300 - 302
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    The purpose of work is to assess adhesion between underfill resins and organic passivation layers using fracture mechanics. We are particularly interested in examining the utility of two types of double cantilever beam specimens: a short, thick double cantilever beam (DCB) specimen versus a long, slender asymmetric double cantilever beam specimen (ADCB) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.