2013 14th International Workshop on Microprocessor Test and Verification

11-13 Dec. 2013

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  • [Front cover]

    Publication Year: 2013, Page(s): C4
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  • [Title page i]

    Publication Year: 2013, Page(s): i
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  • [Title page iii]

    Publication Year: 2013, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2013, Page(s): iv
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  • Table of contents

    Publication Year: 2013, Page(s):v - vi
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  • Preface

    Publication Year: 2013, Page(s): vii
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  • Conference Organization

    Publication Year: 2013, Page(s): viii
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  • Program Committee

    Publication Year: 2013, Page(s): ix
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  • Reviewers

    Publication Year: 2013, Page(s): x
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  • Acknowledgment

    Publication Year: 2013, Page(s): xi
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  • Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques

    Publication Year: 2013, Page(s):3 - 7
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    When developing a new architecture with a new programming model, not only must performance be taken into account, but the programming model itself must also be validated, in order to ensure that software will run correctly and with sufficient efficiency. In this paper, we describe how we applied rapid prototyping techniques to model a new network switch architecture. By concentrating on functional... View full abstract»

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  • Modified Condition Decision Coverage: A Hardware Verification Perspective

    Publication Year: 2013, Page(s):8 - 13
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    Verification is a critical phase of the development cycle. It confirms the compliance of a design implementation with its functional specification. Coverage measures the progress of the verification plan. Structural coverage determines the code exercised by the functional tests. Modified Condition Decision Coverage (MC/DC) is a structural coverage type. This paper compiles a comprehensive overview... View full abstract»

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  • Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System

    Publication Year: 2013, Page(s):14 - 18
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    The Samsung reconfigurable processor (SRP) is developed to accelerate multimedia applications such as video decoding, audio decoding, and image processing. Owing to coarse-grained reconfigurable array (CGRA) acceleration via software (SW) pipelining and application-specific intrinsic instructions, SRP outperforms other digital signal processors (DSPs) in these application domains. In addition, rec... View full abstract»

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  • Measuring the Gain of Automatic Debug

    Publication Year: 2013, Page(s):19 - 22
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    The purpose of regression testing is to quickly catch any deterioration in quality of a product under development. The more frequently tests are run, the earlier new issues can be detected resulting in a larger burden for the engineers who need to manually debug all test failures, many of which are failing due to the same underlying bug. However, there are software tools that automatically debug t... View full abstract»

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  • Proving QBF-hardness in Bounded Model Checking for Incomplete Designs

    Publication Year: 2013, Page(s):23 - 28
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (210 KB) | HTML iconHTML

    Bounded Model Checking (BMC) is a major verification technique for finding errors in sequential circuits by unfolding the design iteratively and converting the BMC instances into Boolean satisfiability (SAT) formulas. Here, we consider incomplete designs (i.e. those containing so-called black boxes) where the verification task is to prove unrealizability of a property. A property is called unreali... View full abstract»

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  • Secure and Trusted SoC: Challenges and Emerging Solutions

    Publication Year: 2013, Page(s):29 - 34
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (758 KB) | HTML iconHTML

    Over the ages, hardware components, platforms and supply chains have been considered secure and trustworthy. However, recent discoveries and reports on security vulnerabilities and attacks in microchips and circuits violate this hardware root of trust. System-on-Chip (SoC) design based on reusable hardware intellectual property (IP) is now a pervasive design practice in the industry due to the dra... View full abstract»

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  • Practical Security Validation

    Publication Year: 2013, Page(s):35 - 38
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (126 KB) | HTML iconHTML

    Attackers are increasingly making use of unintended hardware or firmware behavior to build exploits. To minimize the likelihood of these attacks and to meet their security objectives, hardware products are adopting secure development processes, including performing security validation of components critical to enforcing these objectives. Despite the increasing visibility of hardware security issue... View full abstract»

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  • Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation

    Publication Year: 2013, Page(s):39 - 44
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (343 KB) | HTML iconHTML

    Granularity of transactions, which are initiated by the Programmer's View (PV) models, has high impact on the simulation speed of Virtual Platforms (VP). Since PV models are intended to run at high simulation speed, hardware parameters such as data bus width should not slow-down the simulation speed of the PV-level abstracted transactions. Hardware parameters should be taken into account only to t... View full abstract»

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  • Communication Alternatives Exploration in Model-Driven Design of Networked Embedded Systems

    Publication Year: 2013, Page(s):45 - 51
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (884 KB) | HTML iconHTML

    The design of next-generation networked embedded systems requires to take into account the way in which they exchange information together to provide the desired functionality. In fact, communication patterns and network topology affect the implementation of HW and SW aspects of the nodes and their performance, for this reason the communication infrastructure is becoming a true design space dimens... View full abstract»

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  • On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors

    Publication Year: 2013, Page(s):52 - 57
    Cited by:  Papers (8)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (262 KB) | HTML iconHTML

    When the result of a previous instruction is needed in the pipeline before it is available, a “data hazard” occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic; its test can hardly be ... View full abstract»

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  • IP Testing for Heterogeneous SOCs

    Publication Year: 2013, Page(s):58 - 61
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (127 KB) | HTML iconHTML

    The verification methodology world has progressed spectacularly during the last decade, with increasingly sophisticated techniques and frameworks for driving test stimulus into the device under test. Frequently, however, the focus of these methodology improvements is IP-level verification (i.e., just one part of an overall system or SOC). The last few generations of AMD products combined multi-cor... View full abstract»

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  • Dynamic Selection of Trace Signals for Post-Silicon Debug

    Publication Year: 2013, Page(s):62 - 67
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (731 KB) | HTML iconHTML

    Post-silicon validation is one of the most expensive and complex tasks in today's System-on-Chip (SoC) design methodology. A major challenge in post-silicon debug is limited observability of the internal signals. Existing approaches address this issue by selecting a small set of useful signals. These signal states are stored in an on-chip trace buffer during execution. The applicability of existin... View full abstract»

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  • Automatic Network Protocol Synthesis from UML Sequence Diagrams

    Publication Year: 2013, Page(s):68 - 73
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (986 KB) | HTML iconHTML

    This paper presents a methodology to automatically generate SystemC protocol implementation, starting from its specification given through UML sequence diagrams. The methodology merges such diagrams into a single one, which is then used to generate the SystemC code. Two algorithms are proposed for the merging and refinement step, respectively. SCNSL network simulator is exploited to simulate the g... View full abstract»

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  • Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution

    Publication Year: 2013, Page(s):74 - 76
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (778 KB) | HTML iconHTML

    Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Le... View full abstract»

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  • An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads

    Publication Year: 2013, Page(s):77 - 82
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (266 KB) | HTML iconHTML

    This paper addresses performance issues encountered in parallel functional gate-level simulation executed on multi-core machine. It demonstrates that a straightforward application of the multi-core simulation on a multi-core machine does not improve simulation performance. This is due to unbalanced partitioning, lack of sufficient concurrency in the design partitions, overhead due to communication... View full abstract»

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