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Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668)

21-23 June 2000

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  • Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668)

    Publication Year: 2000
    Request permission for commercial reuse | PDF file iconPDF (200 KB)
    Freely Available from IEEE
  • A methodology of implementing medium access protocols using a general parameterized architecture

    Publication Year: 2000, Page(s):2 - 7
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB)

    The aim of rapid development of communication systems is to automate the process of transforming the high level description of a protocol into hardware and software that would implement the actual system. This paper describes a methodology used to implement medium access protocols based on a microprocessor core and a general parameterized architecture which contains configurable hardware blocks th... View full abstract»

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  • Design space exploration for hardware/software codesign of multiprocessor systems

    Publication Year: 2000, Page(s):8 - 13
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB)

    We present a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The ... View full abstract»

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  • Efficient modeling of preemption in a virtual prototype

    Publication Year: 2000, Page(s):14 - 19
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (134 KB)

    A virtual prototype combines a hardware model with hardware/software cosimulation to support the development and debugging of embedded software before a hardware prototype is available. Existing techniques for hardware/software cosimulation execute the software either on an instruction set simulator for accuracy or on the simulator host processor for increased performance. On the host processor ti... View full abstract»

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  • Combining virtual benchmarking with rapid system prototyping for real-time embedded multiprocessor signal processing system codesign

    Publication Year: 2000, Page(s):20 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (109 KB)

    The codesign of embedded real-time signal processing systems is complex. The use of commercial-off-the-shelf (COTS) multiprocessor (MP) hardware and software can reduce codesign complexity. Further complexity reduction can be obtained with emerging rapid system prototyping (RSP) frameworks, which can generate deployable code by leveraging vendor communication and computation libraries. However, th... View full abstract»

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  • A risk assessment model for software prototyping projects

    Publication Year: 2000, Page(s):28 - 33
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    Software prototyping processes have contributed to develop cheaper, faster and more reliable products. However, despite the advances in technology, little progress has been done in improving the management of software prototyping development projects. Research shows that 45 percent of all the causes for delayed software deliveries are related to organizational issues (Van Genuchten, 1991). This pa... View full abstract»

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  • Processor models for retargetable tools

    Publication Year: 2000, Page(s):34 - 39
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (133 KB)

    This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a generic way. The processor models are written in a language called Sim-nML which is powerful enough to capture the instruction set architecture of a processor We describe a few tools in this paper which can be retargeted to ... View full abstract»

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  • MODUS: integrated behavior-oriented model for rapid prototyping

    Publication Year: 2000, Page(s):40 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (191 KB)

    This paper presents a unified behavior model for digital system (MODUS) that combines both the reactive and the transformational-or procedural-paradigms. The model is the core of an integrated development environment for safety critical applications, designed for rapid prototyping. MODUS includes distinctive features, such as minimum cause-effect delays and uncertain states, seeking accurate model... View full abstract»

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  • Equivalence checking of two Statechart specifications

    Publication Year: 2000, Page(s):46 - 51
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (189 KB)

    In this paper we give a process algebraic semantics for Statechart via a translation into algebra of communicating shared resources (ACSR). Also, we propose a formal verification method for Statechart specifications by showing an equivalence relationship between two Statechart specifications. This makes it possible to combine the advantages of a graphical language with the rigor of process algebra... View full abstract»

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  • Intuitive design of complex real-time control systems

    Publication Year: 2000, Page(s):52 - 57
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (187 KB)

    Designing complex dynamic systems usually involves several iterations. In each of these steps, the system specifications have to be verified and conflicts have to be detected early enough to influence the ongoing fabrication. Classical simulation tools often fail to give answers in time because several simulations are necessary to check the influence of different design parameters and to recognize... View full abstract»

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  • Cycle-true simulation of the ST10 microcontroller including the core and the peripherals

    Publication Year: 2000, Page(s):60 - 65
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (151 KB)

    With the rising complexity of electronic systems, containing more and more hardware and software parts, it becomes necessary to simulate simultaneously, hardware and software at whatever abstraction level. These simulation techniques, called cosimulation, require fast and flexible simulators. We introduce the elaboration of a microcontroller simulator including the core and the peripherals for an ... View full abstract»

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  • Hardware/software co-design of a Java virtual machine

    Publication Year: 2000, Page(s):66 - 71
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (174 KB)

    We discuss the initial results of research into the development of a hardware/software co-design of the Java virtual machine. The design considers a complete Java virtual machine with full functionality expected to run with the same capabilities as a fully software Java virtual machine. We address issues such as why a partial hardware implementation is suitable, the challenges in realizing this go... View full abstract»

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  • Emulator environment based on an FPGA prototyping board

    Publication Year: 2000, Page(s):72 - 77
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB)

    We describe an emulator environment based on an FPGA prototyping board. This emulator environment is for functional verification of a multimedia processor we are developing and for software development and debugging of its application programs. For these purposes, the emulator environment includes a debugging network and provides virtual wires and some utilities, board control functions, and a vir... View full abstract»

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  • A comprehensive prototyping-platform for hardware-software codesign

    Publication Year: 2000, Page(s):78 - 82
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    We present a flexible, yet cost-effective prototyping platform for hybrid hardware/software systems. Our approach is based on combining off-the-shelf hardware components with custom software to arrive at an encompassing solution. We address the hybrid nature of the problem by tightly coupling a conventional processor with configurable logic on a single PCI expansion card. View full abstract»

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  • Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems

    Publication Year: 2000, Page(s):84 - 89
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB)

    Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP), however, existing dataflow design tools are limited in their ability to effectively handle dynamic application behavior. We develop efficient quasi-static scheduling techniques for a broad class of dynamically-reconfigurable dataflow specifications. We use a C... View full abstract»

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  • A design methodology for hardware prototyping of integrated AC drive control: application to direct torque control of an induction machine

    Publication Year: 2000, Page(s):90 - 95
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (341 KB)

    This paper presents a top-down methodology for hardware rapid prototyping of integrated alternating current (AC) drive control, based on hardware description languages (HDLs). This methodology is a set of procedures and computer aided design tools to optimize development time, final product cost and reusability of the digital electronic system design. The use of HDLs provides continuous checking o... View full abstract»

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  • Speeding up hardware prototyping by incremental simulation/emulation

    Publication Year: 2000, Page(s):98 - 102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB)

    We describe a method for the automatic construction of a testbench, able to dynamically communicate a standard VHDL simulator with a logic emulator by means of text files. The proposed approach significantly reduces turn-around times in an emulation based rapid system prototyping environment. In this way, time-consuming logic synthesis and technology mapping steps are moved, in the design cycle, a... View full abstract»

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  • Mapping a high-speed wireless communication function to the reconfigurable J-platform

    Publication Year: 2000, Page(s):103 - 108
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (207 KB)

    We map a software radio function to a coarse grain platform, namely the J-platform. In our previous work the J-platform was based on two types of cells, namely the MA PLUS, which is an enhanced multiply-add cell, and the UNL, a Universal NonLinear cell. We introduce one more cell, namely the DF cell, which is a Data Fabric cell. These three cells account for the versatility of the approach and pro... View full abstract»

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  • A prototype of an AAL for high bit rate real-time data transmission system over ATM networks using a RSE CODEC

    Publication Year: 2000, Page(s):109 - 114
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (219 KB)

    This work introduces a prototype of an ATM Adaptation Layer (AAL) with forward error correction (FEC) to serve the problems raised by high and variable bit rate real-time data transmission systems (for example studio/video applications) over ATM networks. To match the high bandwidth requirements at real-time and to minimize the implementation resources an encapsulated coding system is introduced. ... View full abstract»

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  • The FLYSIG prototyping approach

    Publication Year: 2000, Page(s):115 - 120
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (173 KB)

    We present a customized approach to rapid prototyping based on a new chip design. The chip is named FLYSIG and adapts the prototyping architecture to the target architecture and the application domain in view. The chip architecture is scalable according to the requirements of arithmetic operators and interconnection flexibility. The prototyping chip is configurable in terms of operator functionali... View full abstract»

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  • A Verilog to C compiler

    Publication Year: 2000, Page(s):122 - 127
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    This paper describes a compiler which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native-mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics of Verilog, and also performs logic minimisation. Buses of up to 32 or 64 bits can be modelled as C integers, whereas larger buse... View full abstract»

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  • Using MetaScribe to prototype a UML to C++/Ada95 code generator

    Publication Year: 2000, Page(s):128 - 133
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB)

    The use of program generation from graphical representations like UML is increasing in software projects. The notion of hypergenericity is being posited to improve program generators. This paper presents MetaScribe, a tool designed to build program generators, which provides guidelines to program generator designers and has enhanced facilities for reusability. An example illustrates the use of Met... View full abstract»

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  • An evaluation of code generation strategies targeting hardware for the rapid prototyping of SDL specifications

    Publication Year: 2000, Page(s):134 - 139
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (198 KB)

    The specification of an embedded system at the system level, together with co-joint hardware/software synthesis, is a goal of many rapid prototyping projects. SDL has been proposed as a formal and abstract specification language that is well-suited for this purpose. In the automated generation of hardware, however, SDL's asynchronous communication model (directly implemented in the so-called serve... View full abstract»

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  • Integration and evolution of model-based tool prototypes

    Publication Year: 2000, Page(s):142 - 147
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    Model-based software prototyping enables the effective construction of design tools for new system design approaches in a very short time. In this paper, we show that explicit interface modelling is well-suited to integrate such prototyped tools into design environments. In addition, we point out how our model-based generative approach supports the evolution of prototypes very well. We present the... View full abstract»

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  • Coprocessor synthesis of multirate system using static scheduling theory

    Publication Year: 2000, Page(s):148 - 153
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB)

    Presents a way to perform hardware/software partitioning of multirate systems based on static priority scheduling theory. The problem is described by a set of interacting concurrent tasks. Each task is characterized by the lower bound on the time between successive arrivals of task, a deadline and a dataflow graph describing the computation to be performed on each invocation. All the tasks are imp... View full abstract»

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