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Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on

Date 23-25 April 2014

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Displaying Results 1 - 25 of 78
  • [Front cover]

    Publication Year: 2014 , Page(s): c1
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  • [Title page]

    Publication Year: 2014 , Page(s): 1
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  • [Copyright notice]

    Publication Year: 2014 , Page(s): 1
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  • Foreword to the 17th IEEE DDECS symposium

    Publication Year: 2014 , Page(s): 1
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  • Symposium committees

    Publication Year: 2014 , Page(s): 1
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  • Table of contents

    Publication Year: 2014 , Page(s): 1 - 4
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  • Detection & diagnostics in today's advanced technology nodes

    Publication Year: 2014 , Page(s): 9
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  • Automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems

    Publication Year: 2014 , Page(s): 10
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  • Design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications

    Publication Year: 2014 , Page(s): 11
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  • SiP design flow and 3D DRC for MEMS

    Publication Year: 2014 , Page(s): 12 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1259 KB) |  | HTML iconHTML  

    The contribution will describe in detail recent development related to the integration of MEMS into a SiP design flow. A key step in implementing system-level simulation is the translation of the physical behavior of the constitutive components in a system from the more fine-grained continuum level to more abstract, coarse grained models. An important challenge is the preservation of accuracy from fine-grained simulation to a degree that is deemed adequate. In order for the simulator to run in a reasonable time, the system-level model should only include the degrees of freedom (DOF) necessary to capture the relevant physics. Very handy in this sense are methods of model-order reduction (MOR), which under certain conditions enable almost automatic transfer from the continuum level simulation up to the behavioral models with minimal loss of accuracy. View full abstract»

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  • Development of 3D space partitioning and design rule check for smart system solutions

    Publication Year: 2014 , Page(s): 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (105 KB)  

    In 2013 the microelectronic industry has posted record sales with a healthy growth of more than 7%. The key to this trend is the vision that microelectronics is an enabler for many solutions to the 21st century society challenges. These range from infrastructure, health, transport, energy, security, communications and knowledge transfer. Services with embedded modern technologies have enabled emerging economies to leapfrog traditional development steps in an ever increasing number of sectors. Also, 45% of the economic growth of the OECD economies since 1985 is due to increased productivities thanks in no small measure to the electronic technology. View full abstract»

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  • Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

    Publication Year: 2014 , Page(s): 15 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3573 KB) |  | HTML iconHTML  

    In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes. View full abstract»

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  • Automatically connecting hardware blocks via light-weight matching techniques

    Publication Year: 2014 , Page(s): 21 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (587 KB) |  | HTML iconHTML  

    In modern chip design, many different blocks are assembled in a single chip. Normally, these blocks have been written by different developers or even licensed from other companies. Correctly connecting all blocks is a tedious task. State of the art tools for automatically generating the connections either require identical port-names or additional user input describing the intended connections. View full abstract»

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  • A double-path intra prediction architecture for the hardware H.265/HEVC encoder

    Publication Year: 2014 , Page(s): 27 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (730 KB) |  | HTML iconHTML  

    This paper presents an innovatory approach to the design of the intra prediction architecture for the hardware H.265/HEVC (High Efficiency Video Coding) encoder. As the most of the computational complexity in the intra prediction algorithm is associated with the need to process number of 4×4 Prediction Units (PUs), an independent processing path is proposed for this specific PU size with a separate reconstruction loop. The final result from this path is then incorporated into the second path, independently checking all the remaining PUs. This approach does not entail a significant increase in utilization of hardware resources, while considerably accelerates the encoding. The proposed architecture can operate at 100 MHz for FPGA Aria II devices and at 200 MHz for the TSMC 0.13μm technology. The achieved throughput allows the processing of almost 17.5 and 35 1080p frames per second using FPGA and ASIC technology, respectively. The solution is compliant with the Main, Main 10, and Main Still Picture profiles of the H.265/HEVC standard. View full abstract»

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  • Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic

    Publication Year: 2014 , Page(s): 33 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    Complementing concurrent checking with online testing is crucial for preventing fault accumulation in fault-tolerant systems with long mission times. While implementing a non-intrusive online test is cumbersome in a synchronous environment, this task becomes even more challenging in asynchronous designs. The latter receive increasing attention, mainly due to their elastic timing behaviour; however the issues related with their testing remain a key obstacle for their wide adoption. In this paper we present a novel approach for testing of asynchronous circuits that leverages the redundancy present in the conventional 4-phase protocol for implementing a fully transparent and fully concurrent test procedure. The key idea is to use the protocol's unproductive NULL phase for processing test vectors, thus effectively interleaving the incoming 4-phase data stream with a test data stream in a 2-phase fashion. We present implementation templates for the fundamental building blocks required and give a proof-of-concept by an example application that also serves as a platform for evaluating the overheads of our solution which turn out to be moderate. View full abstract»

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  • Quality assurance in memory built-in self-test tools

    Publication Year: 2014 , Page(s): 39 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault coverage by means of the memory fault simulator. The experimental results show functional benefits and effectiveness of the proposed solutions. View full abstract»

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  • Generic built-in self-repair architectures for SoC logic cores

    Publication Year: 2014 , Page(s): 45 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of system-on-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure. View full abstract»

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  • A 64-MHz∼640-MHz 64-phase clock generator

    Publication Year: 2014 , Page(s): 51 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (570 KB) |  | HTML iconHTML  

    This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18µm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps. View full abstract»

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  • A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

    Publication Year: 2014 , Page(s): 55 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1023 KB) |  | HTML iconHTML  

    This paper presents a design of an area-efficient 10-GHz PLL for source-synchronous, multi-channel applications. To be applied in the multi-channel application, the proposed PLL is implemented without use of any high-cost inductor to minimize silicon area while achieving 10-GHz operation frequency. A modified CML type ring-VCO is used to make the VCO outputs have consistent signal amplitude. The proposed PLL is fabricated in 90-nm low-power CMOS technology. The prototype IC occupies 0.075mm2 of active area and dissipates 87.6-mW power from 1.2-V supply including a 10-GHz clock driver. View full abstract»

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  • Burst-pulse Generator based on transmission line toward sub-MMW

    Publication Year: 2014 , Page(s): 59 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB)  

    A Transmission-line-based Burst-pulse Generator (TPG) is proposed in this paper. The proposed architecture does not consume power in standby stage, so it is more suitable in a pulse system than a continuous wave generator. Also, the center frequency of the pulse can be higher than the Fmax of a CMOS process, since the pulse oscillation need not be sustained. The architecture is modeled and simulated in a 0.18-µm CMOS process, then the performance is compared with a push-push oscillator, which is a conventional method to generate frequency higher than process's Fmax. It is shown that our TPG has better energy conversion efficiency up to a pulse duty cycle of 10%, and the oscillation frequency above 2Fmax of the process is achieved. View full abstract»

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  • A 120V high voltage DAC array for a tunable antenna in communication system

    Publication Year: 2014 , Page(s): 65 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2000 KB) |  | HTML iconHTML  

    This paper presents a integrated high voltage digital-to-analog converter array, which is designed by using a 0.35µm high voltage CMOS technology(AMS H35), and can be applied in high voltage applications up to 120V. The DAC array has 16 high voltage DACs controlled by a digital controller on chip. To fulfil the requirement of communication system with reconfigurable antenna implemented using materials which have voltage dependent capacitance, the DACs are designed to have 8 bits of resolution. In order to improve the accuracy and decrease the required area, each independent DAC is implemented by a low voltage DAC and a high voltage amplifier for boosting the controllable output voltage. Since the current consumption from the high voltage power supply is only 1.28mA, it is possible to be powered by a charge pump which generates high voltage power supply from a battery. The proposed HV DAC array can drive up to 16 individual channels of antenna array with different voltages from 0V to 120V. It will greatly reduce the complexity and cost of mobile applications required high voltage. The feasibility is proved by post-simulation result. View full abstract»

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  • Fast time-parallel C-based event-driven RTL simulation

    Publication Year: 2014 , Page(s): 71 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (339 KB) |  | HTML iconHTML  

    Simulation of the RTL model is one of the first and mandatory steps of the design verification flow. Such a simulation needs to be repeated often due to the changing nature of the design in its early development stages and after consecutive bug fixing. Despite its relatively high level of abstraction, RTL simulation is a very time consuming process, often requiring nightly or week-long regression runs. In this work, we propose an original approach to accelerating RTL simulation that leverages parallelism offered by multi-core machines. However, in contrast to traditional, parallel distributed RTL simulation, the proposed method accelerates RTL simulation in temporal domain by dividing the entire simulation run into independent simulation slices, each to be run on a separate core. It is combined with fast simulation model at ESL level that provides the required initial state for each independent simulation slice. The paper describes the basic idea of the method and provides some initial experimental results showing its effectiveness in improving RTL simulation performance in an automated way. View full abstract»

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  • Lower bounds of the size of Shared Structurally Synthesized BDDs

    Publication Year: 2014 , Page(s): 77 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB) |  | HTML iconHTML  

    A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented as an extension of the SSBDDs, and a method is given to minimize the size of the model. As in case of SSBDDs, the S3BDDs have linear complexity compared to the size of the logic circuit they represent, and they are characterized by the property of one-to-one mapping between the nodes of graphs and signal paths in the circuit. Minimization of S3BDDs makes it possible to get higher rates in fault collapsing, and to speed-up logic simulation as a main tool in delay analysis, fault reasoning and test generation. A lower bound is developed for the size of S3BDDs to evaluate the results of S3BDD synthesis, and it is shown that this bound can be reached rather closely by a straightforward method. Experimental results demonstrate that the S3BDDs represent the most compact BDD based model representing the structure of the digital circuits, which has in average 1.5 times less nodes than the SSBDDs. View full abstract»

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  • BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

    Publication Year: 2014 , Page(s): 83 - 88
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB) |  | HTML iconHTML  

    In this paper we introduce and discuss the Build-Master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time. View full abstract»

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  • Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators

    Publication Year: 2014 , Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    This paper analyses the non-idealities of a second generation current conveyor (CCII) in advanced CMOS technologies. Primary sources of errors in the CCII are identified and their effects are analyzed with respect to its application as an integrator for delta sigma modulators. An improved CCII integrator architecture and a robust calibration algorithm are proposed to negate the CCII errors. The proposed integrator is used in the design of a 4th order CCII based delta sigma modulator, simulation results of which reveal the advantages of proposed solution. The modulator designed in a 1V/90nm technology has a 78/70/46 dB DR and 77/69/45 dB SNDR for bandwidths of 2/4/10 MHz and clock frequency of 160 MHz respectively. View full abstract»

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