17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

23-25 April 2014

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  • [Front cover]

    Publication Year: 2014, Page(s): c1
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  • [Title page]

    Publication Year: 2014, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2014, Page(s): 1
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  • Foreword to the 17th IEEE DDECS symposium

    Publication Year: 2014, Page(s): 1
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  • Symposium committees

    Publication Year: 2014, Page(s): 1
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  • Table of contents

    Publication Year: 2014, Page(s):1 - 4
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  • Detection & diagnostics in today's advanced technology nodes

    Publication Year: 2014, Page(s): 9
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  • Automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems

    Publication Year: 2014, Page(s): 10
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  • Design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications

    Publication Year: 2014, Page(s): 11
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  • SiP design flow and 3D DRC for MEMS

    Publication Year: 2014, Page(s):12 - 13
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1263 KB) | HTML iconHTML

    The contribution will describe in detail recent development related to the integration of MEMS into a SiP design flow. A key step in implementing system-level simulation is the translation of the physical behavior of the constitutive components in a system from the more fine-grained continuum level to more abstract, coarse grained models. An important challenge is the preservation of accuracy from... View full abstract»

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  • Development of 3D space partitioning and design rule check for smart system solutions

    Publication Year: 2014, Page(s): 14
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (105 KB)

    In 2013 the microelectronic industry has posted record sales with a healthy growth of more than 7%. The key to this trend is the vision that microelectronics is an enabler for many solutions to the 21st century society challenges. These range from infrastructure, health, transport, energy, security, communications and knowledge transfer. Services with embedded modern technologies have enabled emer... View full abstract»

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  • Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs

    Publication Year: 2014, Page(s):15 - 20
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (3576 KB) | HTML iconHTML

    In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to s... View full abstract»

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  • Automatically connecting hardware blocks via light-weight matching techniques

    Publication Year: 2014, Page(s):21 - 26
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (587 KB) | HTML iconHTML

    In modern chip design, many different blocks are assembled in a single chip. Normally, these blocks have been written by different developers or even licensed from other companies. Correctly connecting all blocks is a tedious task. State of the art tools for automatically generating the connections either require identical port-names or additional user input describing the intended connections. View full abstract»

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  • A double-path intra prediction architecture for the hardware H.265/HEVC encoder

    Publication Year: 2014, Page(s):27 - 32
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (732 KB) | HTML iconHTML

    This paper presents an innovatory approach to the design of the intra prediction architecture for the hardware H.265/HEVC (High Efficiency Video Coding) encoder. As the most of the computational complexity in the intra prediction algorithm is associated with the need to process number of 4×4 Prediction Units (PUs), an independent processing path is proposed for this specific PU size with a separat... View full abstract»

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  • Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic

    Publication Year: 2014, Page(s):33 - 38
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (190 KB) | HTML iconHTML

    Complementing concurrent checking with online testing is crucial for preventing fault accumulation in fault-tolerant systems with long mission times. While implementing a non-intrusive online test is cumbersome in a synchronous environment, this task becomes even more challenging in asynchronous designs. The latter receive increasing attention, mainly due to their elastic timing behaviour; however... View full abstract»

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  • Quality assurance in memory built-in self-test tools

    Publication Year: 2014, Page(s):39 - 44
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault ... View full abstract»

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  • Generic built-in self-repair architectures for SoC logic cores

    Publication Year: 2014, Page(s):45 - 50
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (409 KB) | HTML iconHTML

    The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of system-on-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR ... View full abstract»

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  • A 64-MHz∼640-MHz 64-phase clock generator

    Publication Year: 2014, Page(s):51 - 54
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (570 KB) | HTML iconHTML

    This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO i... View full abstract»

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  • A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

    Publication Year: 2014, Page(s):55 - 58
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1023 KB) | HTML iconHTML

    This paper presents a design of an area-efficient 10-GHz PLL for source-synchronous, multi-channel applications. To be applied in the multi-channel application, the proposed PLL is implemented without use of any high-cost inductor to minimize silicon area while achieving 10-GHz operation frequency. A modified CML type ring-VCO is used to make the VCO outputs have consistent signal amplitude. The p... View full abstract»

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  • Burst-pulse Generator based on transmission line toward sub-MMW

    Publication Year: 2014, Page(s):59 - 64
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (219 KB) | HTML iconHTML

    A Transmission-line-based Burst-pulse Generator (TPG) is proposed in this paper. The proposed architecture does not consume power in standby stage, so it is more suitable in a pulse system than a continuous wave generator. Also, the center frequency of the pulse can be higher than the Fmaxof a CMOS process, since the pulse oscillation need not be sustained. The architecture is modeled a... View full abstract»

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  • A 120V high voltage DAC array for a tunable antenna in communication system

    Publication Year: 2014, Page(s):65 - 70
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (2000 KB) | HTML iconHTML

    This paper presents a integrated high voltage digital-to-analog converter array, which is designed by using a 0.35μm high voltage CMOS technology(AMS H35), and can be applied in high voltage applications up to 120V. The DAC array has 16 high voltage DACs controlled by a digital controller on chip. To fulfil the requirement of communication system with reconfigurable antenna implemented using mater... View full abstract»

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  • Fast time-parallel C-based event-driven RTL simulation

    Publication Year: 2014, Page(s):71 - 76
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (339 KB) | HTML iconHTML

    Simulation of the RTL model is one of the first and mandatory steps of the design verification flow. Such a simulation needs to be repeated often due to the changing nature of the design in its early development stages and after consecutive bug fixing. Despite its relatively high level of abstraction, RTL simulation is a very time consuming process, often requiring nightly or week-long regression ... View full abstract»

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  • Lower bounds of the size of Shared Structurally Synthesized BDDs

    Publication Year: 2014, Page(s):77 - 82
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (431 KB) | HTML iconHTML

    A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented as an extension of the SSBDDs, and a method is given to minimize the size of the model. As in case of SSBDDs, the S3BDDs have linear complexity compared to the size of the logic circuit they represent, and they are characterized by the property of one-to-one mapping between the nodes of graphs and signal paths in... View full abstract»

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  • BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching

    Publication Year: 2014, Page(s):83 - 88
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    In this paper we introduce and discuss the Build-Master framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluati... View full abstract»

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  • Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators

    Publication Year: 2014, Page(s):89 - 92
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    This paper analyses the non-idealities of a second generation current conveyor (CCII) in advanced CMOS technologies. Primary sources of errors in the CCII are identified and their effects are analyzed with respect to its application as an integrator for delta sigma modulators. An improved CCII integrator architecture and a robust calibration algorithm are proposed to negate the CCII errors. The pr... View full abstract»

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