2014 19th IEEE European Test Symposium (ETS)

26-30 May 2014

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  • [Front cover]

    Publication Year: 2014, Page(s): 1
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  • [Blank page]

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  • [Title page]

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  • [Copyright notice]

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  • ETS 2014 Foreword

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  • Organizing committee

    Publication Year: 2014, Page(s):1 - 3
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  • Steering and program committees

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  • ETS 2013 Best Paper

    Publication Year: 2014, Page(s): 1
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  • TTTC: Test technology technical council

    Publication Year: 2014, Page(s):1 - 3
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  • Sponsors

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  • Major eras of Design for Test

    Publication Year: 2014, Page(s): 1
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (103 KB) | HTML iconHTML

    From writing functional tests to managing design groups to managing major businesses, Dr. Rhines has been personally involved in the evolution of Design for Test. From this perspective, he will describe the driving forces and technologies that changed the way we design products to make them testable, and what will drive change in the future. View full abstract»

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  • Factoring variability in the Design/Technology Co Optimisation (DTCO) in advanced CMOS

    Publication Year: 2014, Page(s): 1
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (143 KB) | HTML iconHTML

    Summary form only given. This paper describes the fully automated GSS tool flow, which bridges the gap between Technology Computer Aided Design (TCAD) at the transistor level, and circuit simulations and verification. The purpose of the tool flow is twofold: (i) to allow rapid simulation-based Design-Technology Co-Optimisation (DTCO) and (ii) to allow generation of accurate compact models for Prel... View full abstract»

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  • Two soft-error mitigation techniques for functional units of DSP processors

    Publication Year: 2014, Page(s):1 - 6
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (551 KB) | HTML iconHTML

    This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic ... View full abstract»

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  • Reducing embedded software radiation-induced failures through cache memories

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (12)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    Cache memories are traditionally disabled in space-level and safety-critical applications, since it was believed that the sensitive area they introduce would compromise the system reliability. As technology has evolved, the speed gap between logic and main memory has increased in such a way that disabling caches slows the code much more than in the past. As a result, the processor is exposed for a... View full abstract»

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  • Detection conditions for errors in self-adaptive better-than-worst-case designs

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (319 KB) | HTML iconHTML

    The rapidly increasing variability in circuit performance in highly scaled technologies has given rise to novel “better-than-worst-case” circuit design methods. They aim to overcome worst-case clock timing requirements by employing a shorter clock period and allowing occasional errors to occur; these are detected and recovered from by low-cost error detection and correction techniques. We investig... View full abstract»

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  • Systematic generation of diagnostic software-based self-test routines for processor components

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (7)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    Recently some fine-grained self-repair techniques for processors have been published that can handle permanent faults in particular components of a processor in-the-field. Unfortunately, the generation of diagnostic tests that can be used in-the-field for fault localization in these components is not solved satisfactorily. A few papers paid attention on improving the diagnostic capabilities of sof... View full abstract»

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  • Diagnosis of multiple faults with highly compacted test responses

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is ro... View full abstract»

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  • Improving polynomial datapath debugging with HEDs

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (452 KB) | HTML iconHTML

    In this paper, we introduce a formal and scalable debugging approach to derive a reduced ordered set of design error candidates in polynomial datapath designs. To make our debugging method scalable for large designs, we utilize a Modular Horner Expansion Diagram (M-HED), which has been shown to be a scalable high level decision model. In our method, we extract data dependency graphs from the polyn... View full abstract»

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  • Test-mode-only scan attack using the boundary scan chain

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (9)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    Boundary-scan is a very popular technology with wide applications in product life cycle that ranges from product design, prototype debugging, production to field service. However, when it comes to securing a product such as smart card, RFID tag, set-top-box, etc., the technology can be targeted by an attacker to reveal the secret information of the chip. In this paper, for the first time, we will ... View full abstract»

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  • A true random number generator with on-line testability

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (249 KB) | HTML iconHTML

    True random number generators (TRNGs) are widely used throughout cryptography. They are used in the challenge response authentication procedures, key generation and for hardening measures against power analysis attacks. An important feature of each TRNG is true randomness. Such randomness can be obtained from random physical effects like noise. In order to make a TRNG usable for different semicond... View full abstract»

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  • A new efficiency criterion for security oriented error correcting codes

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (738 KB) | HTML iconHTML

    Security oriented codes are considered as one of the most efficient countermeasures against fault injection attacks. Their efficiency is usually measured in terms of their error masking probability. This criterion is applicable in cases where it is possible to distinguish between random errors and malicious attacks. In practice, if the induced errors are not fixed for several clock cycles, it is d... View full abstract»

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  • Shadow-scan design with low latency overhead and in-situ slack-time monitoring

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (283 KB) | HTML iconHTML

    Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be per... View full abstract»

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  • Sat-based speedpath debugging using waveforms

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1425 KB) | HTML iconHTML

    A major concern in the design of high performance VLSI circuits is speedpath debugging. This is due to the fact that timing variations induced by process variations and environmental effects are increasing as the size of VLSI circuits is shrinking. In this paper, a speedpath debugging approach based on Boolean Satisfiability (SAT) is proposed. The approach takes waveforms of the signals of a circu... View full abstract»

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  • Smart-hopping: Highly efficient ISA-level fault injection on real hardware

    Publication Year: 2014, Page(s):1 - 6
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    Fault-injection experiments on the instruction-set architecture level are commonly used to analyze embedded software's susceptibility to hardware faults, typically involving a vast number of experiments with systematically varying fault locations and times. Determinism and high performance are the predominant requirements on fault-injection platforms. Injecting faults into a real embedded hardware... View full abstract»

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  • Analysis and mitigation of single event effects on flash-based FPGAS

    Publication Year: 2014, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (705 KB) | HTML iconHTML

    In the present paper, we propose a new design flow for the analysis and the implementation of circuits on Flash-based FPGAs hardened against Single Event Effects (SEEs). The solution we developed is based on two phases: 1) an analyzer algorithm able to evaluate the propagations of SETs through logic gates; 2) a hardening algorithm able to place and route a circuit by means of optimal electrical fi... View full abstract»

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