Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512)

31 Jan.-3 Feb. 2000

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  • Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512)

    Publication Year: 2000
    Request permission for reuse | PDF file iconPDF (121 KB)
    Freely Available from IEEE
  • Parallel architecture for the implementation of the embedded zerotree wavelet algorithm

    Publication Year: 2000, Page(s):3 - 8
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    We propose a parallel architecture for the implementation of the embedded zerotree wavelet (EZW) algorithm, based on the depth-first search (DFS) bit stream (BS) architecture. Using the depth-first search of the wavelet coefficient tree, the wavelet coefficients in the coefficient tree are first partitioned into independent sub-trees. In the case of full parallelism, each of the sub-trees is proce... View full abstract»

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  • Cost/performance tradeoff of n-select square root implementations

    Publication Year: 2000, Page(s):9 - 16
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (99 KB)

    Hardware square-root units require large numbers of gates even for iterative implementations. In this paper we present four low-cost high-performance fully-pipelined n-select implementations (nS-Root) based on a non-restoring-remainder square root algorithm. The nS-Root uses a parallel array of carry-save adders (CSAs). For a square root bit calculation, a CSA is used once. This means that the cal... View full abstract»

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  • On the feasibility of fixed-length block structured architectures

    Publication Year: 2000, Page(s):17 - 25
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (181 KB)

    Scaling contemporary superscalar microarchitectures to higher levels of parallelism in future technologies seems to be impractical due to the increasing complexity. In this paper, we show that a fixed-length block structured instruction set architecture (BSA), is capable of reducing the hardware complexity and is therefore feasible as an alternative architectural paradigm for traditional architect... View full abstract»

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  • The circuit object organisation library

    Publication Year: 2000, Page(s):26 - 33
    Cited by:  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (35 KB)

    The Circuit Object Organisation Library is a C++ class library for developing continuously executing circuit generator programs used in real-time, adaptive reconfigurable computing applications. A C++ program linked with COOL can execute autonomously, since COOL provides a high-speed place and route facility for realising fine grained FPGA circuits from object-oriented structural descriptions. Wit... View full abstract»

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  • Micro-threading: a new approach to future RISC

    Publication Year: 2000, Page(s):34 - 41
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (129 KB)

    This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response to this development we present a new approach to RISC micro-architecture named micro-threading. Micro-threading exploits instruction-level parallelism by multi-threading but where the threads are all assumed to be drawn ... View full abstract»

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  • Dataflow Java: implicitly parallel Java

    Publication Year: 2000, Page(s):42 - 50
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (65 KB)

    Dataflow computation models enable simpler and more efficient management of the memory hierarchy-a key barrier to the performance of many parallel programs. This paper describes a dataflow language based on Java. Use of the dataflow model enables a programmer to generate parallel programs without explicit directions for message passing, work allocation and synchronisation. A small handful of addit... View full abstract»

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  • The architecture of an FPGA-style programmable fuzzy logic controller chip

    Publication Year: 2000, Page(s):51 - 56
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (59 KB)

    In the search for a fuzzy logic equivalent of the FPGA, the authors have developed the design for a programmable fuzzy logic controller chip which can accept up to 4 inputs, provide up to 12 programmable membership functions to fuzzify those inputs, and provide up to 8 programmable singleton values from which an output can be synthesised. Up to 64 rules can be evaluated simultaneously. The analogu... View full abstract»

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  • Adaptive middleware for heterogeneous defence networks-an exploratory simulation study

    Publication Year: 2000, Page(s):57 - 63
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (83 KB)

    This paper presents the design and evaluation through a discrete event simulation of an ODP-based Adaptive Computing Architecture which manages network resources in large-scale heterogeneous error-prone networks. The emphasis is given to network (communication) adaptation of this architecture simulated for an exemplar defence network. The results show that, for this network, the architecture provi... View full abstract»

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  • A scalable re-configurable processor

    Publication Year: 2000, Page(s):64 - 73
    Cited by:  Patents (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (138 KB)

    Several commercial and research projects have produced a variety of 'computing surfaces' based on FPGAs with some interconnection pattern. However, because the majority of these projects have constrained themselves to two-dimensional structures that can be fabricated on a single planar substrate, the interconnect patterns are fixed and severely constrain the ability of a problem to be mapped on to... View full abstract»

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  • Automated component adaptation by forced simulation

    Publication Year: 2000, Page(s):74 - 81
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (103 KB)

    Embedded systems are often designed by experienced designers by interfacing appropriate programmable components to a microprocessor to meet particular design requirements. However, during automated synthesis of these systems, reuse of programmable components hardly takes place. The primary reason is the lack of algorithms that can perform component adaptation like a human designer. In this paper, ... View full abstract»

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  • Reconfigurable computing based on universal configurable blocks-a new approach for supporting performance- and realtime-dominated applications

    Publication Year: 2000, Page(s):82 - 89
    Cited by:  Patents (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    A novel architecture for reconfigurable computing based on a coarse grain FPGA-like architecture is introduced. The basic blocks contain all arithmetical and logical capacities as well as some registers and will be programmable by sequential instruction streams produced by software compiler. Reconfiguration is related to hyper-blocks of instructions. For the composed reconfigurable processors a cl... View full abstract»

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  • Static scheduling for out-of-order instruction issue processors

    Publication Year: 2000, Page(s):90 - 96
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    Superscalar processors strive to increase the number of instructions issued in each processor cycle. Compilers therefore need to expose as much Instruction Level Parallelism (ILP) as possible by using increasingly complex code optimisations. However, the knowledge base of instruction scheduling is focused on in-order instruction issue. It has previously been determined that aggressive static instr... View full abstract»

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  • Fast address-space switching on the StrongARM SA-1100 processor

    Publication Year: 2000, Page(s):97 - 104
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (73 KB)

    The StrongARM SA-1100 is a high-speed low-power processor aimed at embedded and portable applications. Its architecture features virtual caches and TLBs which are not tagged by an address-space identifier. Consequently, context switches on that processor are potentially very expensive, as they may require complete flushes of TLBs and caches. This paper presents the design of an address-space manag... View full abstract»

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  • Author index

    Publication Year: 2000, Page(s): 105
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    Freely Available from IEEE