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Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on

Date 19-22 May 2013

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Displaying Results 1 - 25 of 38
  • [Front cover]

    Publication Year: 2013 , Page(s): C4
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  • [Title page i]

    Publication Year: 2013 , Page(s): i
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  • [Title page iii]

    Publication Year: 2013 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2013 , Page(s): iv
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  • Table of contents

    Publication Year: 2013 , Page(s): v - vii
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  • Welcome Message from the Chairs

    Publication Year: 2013 , Page(s): viii - ix
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  • Symposium Organizing Committee

    Publication Year: 2013 , Page(s): x
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  • Technical Program Committee

    Publication Year: 2013 , Page(s): xi
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  • Reviewers

    Publication Year: 2013 , Page(s): xii
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  • Steering Committee

    Publication Year: 2013 , Page(s): xiii
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  • Conference sponsors

    Publication Year: 2013 , Page(s): xiv
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  • Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS

    Publication Year: 2013 , Page(s): xv
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    Summary form only given, as follows. Process, voltage and temperature (PVT) variations pose major challenges to achieving energy-efficient performance in multi-core & many-core processors and SoC designs in nanoscale CMOS. Aging-induced transistor and interconnect degradations limit power and performance. Impacts of variations and aging are further aggravated in the Near-Threshold Voltage (NTV) operating regime where energy efficiency peaks. Interconnect delays are becoming bottlenecks to efficient global communications across the die. We will discuss variation-tolerant logic and memory design techniques that enable robust operation in nanoscale CMOS. We will present voltage-frequency adaptation and resiliency schemes that can mitigate impacts of dynamic variations and aging. Many-core processor designs that use a mesochronous Network-on-Chip (NoC) mesh to overcome clock distribution and global interconnect challenges will be presented. Opportunities offered by fully asynchronous designs to further improve tolerance to extreme variations will be discussed. View full abstract»

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  • Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages

    Publication Year: 2013 , Page(s): 1 - 7
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (423 KB) |  | HTML iconHTML  

    With the recent advancement of nanometer process technologies and the growing interest in scaled supply voltage operation, we are facing increasing challenges to robust design due to process, voltage, and temperature (PVT) variation. One promising direction is to consider asynchronous pipelines, which eliminate the need for fixed-rate clock distribution. However, while conventional single-rail bundled-data asynchronous pipeline styles can mitigate global and spatial variations by closely placing the delay elements to their corresponding pipeline stages, random variations are currently not effectively handled. In particular, timing margins must be added to the matched delay elements in each stage, resulting in reduced performance and increased leakage power consumption. Building upon a well-known asynchronous pipeline, MOUSETRAP, this paper proposes a scheme to mitigate the impact of random PVT variations over a range of supply voltages. We introduce the notion of soft latching for asynchronous pipelines: allowing data registers to latch their incoming data during a wider sampling window. As a result, the pipeline operates correctly even with random PVT variation-induced delay mismatch between a bundled delay and its corresponding pipeline stage. However, the inclusion of soft latching can exacerbate hold time violations, these are mitigated through a novel protocol modification. The new asynchronous soft-latching scheme shows significant energy-efficiency and performance improvement over the conventional margining approach, it also robustly operates down to 0.3V even in the presence of random process variations. View full abstract»

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  • A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems

    Publication Year: 2013 , Page(s): 8 - 15
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    This paper introduces a low-energy variation-tolerant asynchronous ternary content-addressable memory (TCAM) for Network Intrusion Detection Systems (NIDS). The proposed special-purpose TCAM can detect packet payloads as "virus free" by inspecting only a few bytes. Hence, it adaptively cancels unnecessary searches, leading to greatly reduction in the search delay time and energy dissipation. For timing robustness with low area overhead, a word circuit that stores a virus pattern is designed based on both a quasi-delay insensitive (QDI) and a bundled-data techniques. The QDI word circuit is realized by combining complementary word circuits for only a small portion of the TCAM that is sensitive to delay variations. For performance evaluation, a probability of the virus detection is calculated using a set of real packet traces from MIT DARPA. A 2048 × 128-byte asynchronous TCAM is designed using TSMC 65nm CMOS technology. The energy dissipation is 93.1% lower and the cycle time is 52.4% lower than those of a deep-pipelined synchronous TCAM with a comparable area. It is also demonstrated that the proposed TCAM tolerates up to 47% variations (3s) of threshold voltages. View full abstract»

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  • Capacitor Discharging Through Asynchronous Circuit Switching

    Publication Year: 2013 , Page(s): 16 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (501 KB) |  | HTML iconHTML  

    Operation elasticity due to the proportional relationship between energy and switching activity of asynchronous circuits has made them hugely attractive for energy harvesting systems. Using asynchronous logic makes it possible to minimize the power regulation efforts and instead, supply the circuit directly from the energy storage while a proper load scheduler is employed. In this context, the switching behaviour of the asynchronous load while it is powered by a capacitor becomes crucial to the effectiveness of the scheduler. This paper examines the relationship between the switching behaviour of a self-timed digital circuit and the dynamic characteristic of the voltage on the capacitor while the circuit is powered by the capacitor. For this purpose, a sample system is considered that consists of an initially charged capacitor which is discharged through the switching of a ring oscillator. Closed-form expressions are obtained for the supply voltage of the ring oscillator over time as it operates. Our analytical solution shows maximum 4.6% and 5.4% difference from experimental results in super and sub-threshold regions respectively. The experimental results are captured from a chip fabricated at 180nm technology node. View full abstract»

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  • Modular Redundancy in a GALS System Using Asynchronous Recovery Links

    Publication Year: 2013 , Page(s): 23 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB) |  | HTML iconHTML  

    In this paper we describe a new design approach for fault-tolerant globally asynchronous locally synchronous (GALS) systems using triple modular redundancy. The paper proposes a recovery and voting mechanism that relies on asynchronous, delay-insensitive links for state exchange. Thereby the replicated module copies remain fully timing-independent and only need to be locally synchronized. This allows for extremely flexible module partitioning and placement: Triplicated modules could be arranged on a single die, or be mapped to three separate chips to minimize the risk of two copies failing at the same time. In the first part of the paper we discuss the general concept of the recovery mechanism and the requirements for the design of the GALS modules to ensure replica determinism. The second part of the paper then presents the implementation of a lightweight recovery controller, which consists of both synchronous and asynchronous components. To access the internal state of a module we re-use the scan chains, which are typically included in every synchronous circuit for testing purposes. The robustness of our solution is verified by exhaustive fault-injection experiments. View full abstract»

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  • An SET Tolerant Tree Arbiter Cell

    Publication Year: 2013 , Page(s): 31 - 39
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (585 KB) |  | HTML iconHTML  

    Due to their inherently in deterministic behavior arbiters cannot simply be made fault tolerant by replication. We present an in-depth analysis of a tree arbiter cell with respect to possible faults and failure modes. Based on these results we devise a fault tolerant implementation of this cell that carefully avoids all single points of failure and can hence withstand transient faults as well as bit flips in its stateful elements. We verify the fault tolerance of our implementation by means of model checking and compare its overheads and performance penalties with a TMR-based solution. While the validation confirms that our approach is indeed suitable for use within an overall fault tolerance concept, the penalties turn out to be lower than for a comparable TMR approach. View full abstract»

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  • NanoMesh: An Asynchronous Kilo-Core System-on-Chip

    Publication Year: 2013 , Page(s): 40 - 49
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    Innovative asynchronous circuits are central to the Ethernet switch chips from Intel's Switch and Router Division (formerly Fulcrum Microsystems). These circuits are complex, and it can be hard to gauge their benefits since there are few direct comparisons. For this paper, we apply the technology and tool flow developed for these commercial products to a familiar benchmark: a network of general purpose processors on a chip. The processor is a single-issue 32-bit integer RISC core, a from-scratch implementation mostly compatible with the MIPS R3000. The network uses a 16-port 32-bit fully connected Nexus crossbar. We achieve greater scalability by linking these crossbars in a 2D mesh with clusters of 8 cores and 4 cardinal and 4 diagonal links per tile. Each core has 64KB of local memory and can access the memory of any other core in the mesh. Our design makes heavy use of the Proteus synthesis, place & route flow, as well as existing custom cells. It required only a few man-months of effort to develop a complete gate-level design and physical floor-plan which can run simple C programs such as Dhrystone. A few more man-months will produce a test chip, expected in 2013. View full abstract»

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  • An Asynchronous Dataflow Signal Processing Architecture to Minimize Energy per Op

    Publication Year: 2013 , Page(s): 50 - 57
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    Recent data shows that Dennard's law, which dictates the energy efficiency of digital transistors as their size shrinks, has failed in sub-100nm processes. New architectural paradigms need to be pursued to address the ever-increasing energy efficiency demands of commercial and military systems. This work presents a new dataflow architecture implemented with asynchronous circuits and laid out in a 45nm process. The work is derived from our previous work in developing a fully programmable architecture we call the Field Programmable Compute Array (FPCA), which was implemented using synchronous circuits. We present the results of our work to implement a FIR filter constructed using this paradigm. The asynchronous results are compared with a synchronous version of the same filter that was built using a standard-clocked digital-logic automated design flow. We simulated using an extracted layout and the results show significant improvement in cycle time, frequency and efficiency. The asynchronous pipeline has an overall efficiency improvement of 6.57 times that of the synchronous pipeline. We also show that in the asynchronous design we were able to scale the supply voltage from nominal down to 200mV, which results in even greater efficiency. This paper includes a discussion regarding the property of dataflow elasticity, which is needed for full programmability. Finally, we detail how to construct the circuits necessary to create this new type of pipeline. View full abstract»

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  • cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells

    Publication Year: 2013 , Page(s): 58 - 66
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB) |  | HTML iconHTML  

    Asynchronous circuits are an attractive option to overcome many challenges currently faced by chip designers, such as increased process variation. However, the lack of CAD tools to generate asynchronous circuits limits the adoption of this promising technology. In this absence of CAD tools, the most time consuming part of chip design is the back-end (physical design) effort. We propose a complete design infrastructure to physically implement an asynchronous digital net list with orders of magnitude time savings over expert human effort. The core of this flow is the ability to generate customized logic that is compatible with available ASIC flows. We evaluate our flow against several asynchronous circuit benchmarks for which full custom physical implementations exist. Compared to hand-optimized custom designs, our flow produces layout that has, on average, a 51% area overhead, with a 12% increase in energy and a 9% increase in delay. View full abstract»

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  • Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation

    Publication Year: 2013 , Page(s): 67 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    Asynchronous designs are usually composed of conditional circuits. The analysis of these circuits is complex especially when delay variability is considered. In this paper, we design and implement a model-based Statistical Static Timing Analysis "SSTA" framework that is able to analyze conditional asynchronous circuits in efficient time. First, the paper introduces how the conditional circuits can be modeled, and then it shows how this model can be used to realize the SSTA analysis. View full abstract»

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  • Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear Programing

    Publication Year: 2013 , Page(s): 75 - 82
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (402 KB) |  | HTML iconHTML  

    This paper presents accurate performance bounds for conditional asynchronous circuits which demonstrate mode-based behavior. Analyzing the performance of these circuits is challenging as the critical paths cannot be identified without knowing the exact sequence of modes of operations which is generally unknown during design time. We used Markov chain processes to model mode switching and unique choice Petri nets to model performance. We adopt a performance analysis scheme based on decomposing the behavior of the Petri net into marked graph components to reason about performance. The bounds are derived using linear programming based on the probability matrix of the Markov chain and can be incorporated in performance-aware optimization of conditional asynchronous circuits. To evaluate the accuracy of the bounds, the theory is applied to a new set of benchmark circuits that includes randomly generated conditional circuits (ISCAS89a) and an industrially-inspired example. View full abstract»

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  • GALS Design for Spectral Peak Attenuation of Switching Current

    Publication Year: 2013 , Page(s): 83 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1038 KB) |  | HTML iconHTML  

    Digital circuits often suffer from the switching noise when synchronized by a global clock. This work investigates the spectral peak attenuation of the switching current by applying Globally Asynchronous Locally Synchronous (GALS) design. It is theoretically proven that, in particular for a plesiochronous design with M clock domains, an attenuation of up to 20logM dB can be achieved at lower order harmonics of the clock frequency. Power-consumption balanced GALS partitioning is found to be preferred for spectral noise attenuation, since it provides robustness against the current shape variations in individual blocks. Experiments on a 130-nm CMOS synchronous/GALS dual-core FMCW-RADAR chip, named Lighthouse, have been performed. Comparing with the synchronous design, on the on-chip power supply, a spectral peak attenuation of 12.29 dB at the fundamental clock frequency can be measured for the power balanced GALS design with five plesio-chronous clocks. View full abstract»

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  • Distributed Phase Correction Technique

    Publication Year: 2013 , Page(s): 91 - 98
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    We broadly use the term phase alignment to encompass the repositioning of edges in one signal with respect to edges in another ``reference'' signal. This paper introduces a phase alignment block, and exemplifies its operation in a couple of separate contexts. A recurring theme in these contexts is the use of phase alignment via temporal- and spatial-mixing/multiplexing. We term both forms of mixing as performing ``distributed'' phase correction. The distinguishing feature in these contexts is the employment of the phase alignment block to either enhance or add additional functionality to conventional timing blocks. In the context of a voltage controlled delay line for a delay locked loop (DLL), we examine how the distributed mixing reduces both jitter and duty cycle disturbances. And in the context of a phase error detector and correction block for a phase locked loop (PLL), we examine how distributed coupling adds a design dimension in terms of trading off phase correction gain versus cycle jitter. View full abstract»

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  • A Self-Timed Ring Based True Random Number Generator

    Publication Year: 2013 , Page(s): 99 - 106
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB) |  | HTML iconHTML  

    Self-timed rings are oscillators in which several events can evolve evenly-spaced in time thanks to analog effects inherent to the ring stage structure. One of their interesting features is that they provide precise high-speed multiphase signals. This paper presents a true random number generator that exploits the jitter of events propagating in a self-timed ring with a high entropy. Designs implemented in Alter a Cyclone III and Xilinx Virtex 5 devices provide high quality random bit sequNIST SP 800-22 statistical testsences passing FIPS 140-1 and NIST SP 800-22 statistical tests at a high bit rate. View full abstract»

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