2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

8-10 April 2013

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  • [Front cover]

    Publication Year: 2013, Page(s): c1
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  • [Title page]

    Publication Year: 2013, Page(s): 1
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  • 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) [Copyright notice]

    Publication Year: 2013, Page(s): 1
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  • Foreword to the 16th IEEE DDECS Symposium

    Publication Year: 2013, Page(s): 1
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  • Symposium committees

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  • Table of contents

    Publication Year: 2013, Page(s):1 - 4
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  • Hardware-Software Co-Visualization: Developing systems in the holodeck

    Publication Year: 2013, Page(s):1 - 4
    Cited by:  Papers (2)
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  • Approximate computing for energy-efficient error-resilient multimedia systems

    Publication Year: 2013, Page(s):5 - 6
    Cited by:  Papers (2)  |  Patents (1)
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  • Creating options for 3D-SIC testing

    Publication Year: 2013, Page(s): 7
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  • Interpolation-based model checking for efficient incremental analysis of software

    Publication Year: 2013, Page(s):8 - 9
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (94 KB) | HTML iconHTML

    Verification based on model checking has recently obtained an important role in certain software engineering tasks, such as developing operating system device drivers. This extended abstract discusses how model checking can be made more efficient by using the structure from program function calls. We use this idea in two orthogonal ways, both of which fundamentally depend on automatically summariz... View full abstract»

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  • Cross-layer resilient system design

    Publication Year: 2013, Page(s): 10
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    Summary form only given. Improvements in chip manufacturing technology have propelled an astonishing growth of computing systems which are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. At the device level, as the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and avail... View full abstract»

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  • Hardware acceleration in computer networks

    Publication Year: 2013, Page(s): 11
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    Summary form only given. Network traffic processing speed is crucial in most of network devices, because any packet drop can lead to lower quality of network services, affect precise monitoring or disallow detection of security threats. General purpose processors are not able to process all data on high-speed network links. For 100 Gb lines, packet can arrive every 5 ns. Therefore network devices ... View full abstract»

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  • Fault-based attacks on cryptographic hardware

    Publication Year: 2013, Page(s):12 - 17
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    Mobile and embedded systems increasingly process sensitive data, ranging from personal information including health records or financial transactions to parameters of technical systems such as car engines. Cryptographic circuits are employed to protect these data from unauthorized access and manipulation. Fault-based attacks are a relatively new threat to system integrity. They circumvent the prot... View full abstract»

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  • Exploring processor parallelism: Estimation methods and optimization strategies

    Publication Year: 2013, Page(s):18 - 23
    Cited by:  Papers (8)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    Former research on automatic exploration of ASIP architectures mostly focused on either the internal memory hierarchy, or the addition of complex custom operations to RISC based architectures. This paper focuses on VLIW architectures and, more specifically, on automating the selection of an application specific VLIW issue-width. An accurate and efficient issue-width estimation strongly influences ... View full abstract»

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  • On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems

    Publication Year: 2013, Page(s):24 - 29
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hard... View full abstract»

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  • Area-speed efficient modular architecture for GF(2m) multipliers dedicated for cryptographic applications

    Publication Year: 2013, Page(s):30 - 35
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    Arithmetic operations over GF(2m) have wide applications in many domains, especially in cryptography. Cryptographic applications of GF(2m) arithmetic units are the most demanding applications. The binary finite field extension multipliers are components of elliptic curve cryptography (ECC) systems and perform crucial operations in the system. In fact all operations in the sys... View full abstract»

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  • On the on-line functional test of the Reorder Buffer memory in superscalar processors

    Publication Year: 2013, Page(s):36 - 41
    Cited by:  Papers (2)
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    The Reorder Buffer (ROB) is a key component in superscalar processors. It enables both in-order commitment of instructions and precise exception management even in those architectures that support out-of-order execution. The ROB architecture typically includes a memory array whose size may reach several thousands of bits. Testing this array may be important to guarantee the correct behavior of the... View full abstract»

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  • Fault collapsing of multi-conditional faults

    Publication Year: 2013, Page(s):42 - 47
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (198 KB) | HTML iconHTML

    Numerous new multi-conditional fault models have been proposed in the last years. In combination with the increasing complexity of today's designs these new fault models cause a tremendous increases of the ATPG-runtime. In this paper we present a novel fault collapsing scheme for multi-conditional faults. The objective is to significantly reduce the fault set and hence reduce runtime for ATPG and ... View full abstract»

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  • Efficient automated speedpath debugging

    Publication Year: 2013, Page(s):48 - 53
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (452 KB) | HTML iconHTML

    Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this paper, an efficient approach to automate speedpath debugging is presented. The approach relies on converting the timing behavior of a circuit and its corresponding timing variations into... View full abstract»

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  • A static analysis approach to data race detection in SystemC designs

    Publication Year: 2013, Page(s):54 - 59
    Cited by:  Papers (4)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (661 KB) | HTML iconHTML

    One of the common methods for system behavior verification and performance estimation is high-level modeling using SystemC. A SystemC design represents parallel components of the system and their interconnections, so it is important to ensure that the design does not have synchronization errors: deadlocks, livelocks, and data races. In this paper we propose a novel approach to data races detection... View full abstract»

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  • Debugging HDL designs based on functional equivalences with high-level specifications

    Publication Year: 2013, Page(s):60 - 65
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (223 KB) | HTML iconHTML

    The increasing complexity of circuits and systems is forcing design specifications to software-like programming languages like C. Since the conversion from software to hardware is a difficult task solved manually, bugs are frequently introduced in the HDL design. Sophisticated automated error localization and correction techniques, i.e. debugging, are a challenge. In this paper a new automated met... View full abstract»

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  • Design of stochastic Viterbi decoders for convolutional codes

    Publication Year: 2013, Page(s):66 - 71
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (990 KB) | HTML iconHTML

    The Viterbi algorithm is widely used to decode convolutional codes. We present an unconventional approach to Viterbi decoder design based on stochastic computing (SC) which represents data by random bit-streams that can be interpreted as probabilities. Stochastic circuits allow many decoding functions to be implemented by simple hardware; e.g., multi-bit multiplication can be realized by an AND ga... View full abstract»

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  • 10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology

    Publication Year: 2013, Page(s):72 - 75
    Cited by:  Papers (5)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter based cascode feedback (Inv-Cascode-TIA) with shunt feedback resistor. The TIA is followed by an one-stage single-ended common-source amplifier (CS), a two-stage differential amplifier and a 50Ω differential output driver to provide a... View full abstract»

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  • Ultra-high bandwidth fully-differential three-stage operational amplifiers in 40nm digital CMOS

    Publication Year: 2013, Page(s):76 - 81
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (415 KB) | HTML iconHTML

    Two three-stage fully differential operational amplifiers designed in 40nm digital CMOS technology are presented. The proposed operational amplifiers are designed to be applied in high speed system on chips (SoCs). The proposed operational amplifiers would find applications in continues time system (CTS) or discrete time system (DTS) according to their own frequency response type, which are discus... View full abstract»

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  • A GHz full-division-range programmable divider with output duty-cycle improved

    Publication Year: 2013, Page(s):82 - 85
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (678 KB) | HTML iconHTML

    This work presents a full-division-range programmable frequency divider with a 50% duty-cycle output. The proposed programmable frequency divider includes a programmable counter (PC) and duty-cycle improved circuit (DCIC) to achieve a full-division-range, low-area, and close-to-50% duty-cycle output from an input clock with an arbitrary duty cycle. A chip was fabricated using a 0.18-μm standard CM... View full abstract»

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